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參數(shù)資料
| 型號(hào)： | C9827JY |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 170K |
| 代理商： | C9827JY |
C9827J
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07107 Rev. **
5/24/2001
Page 16 of 25
CPU_STP# - Assertion (transition from logic ‘1’ to logic ‘0’)
When CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via
assertion of CPU_STP# will be stopped after being sampled by 2 falling CPU clock edges. The final state of the stopped
CPU signals is CPU = high and CPU0# = Low. There is no change to the output drive current values during the stopped
state. The CPU is driven high with a current value equal to (Mult 0 ‘select’) x (Iref), and the CPU# signal will not be
driven. Due to external pulldown circuitry CPU# will be low during this stopped state.
CPU_STP#
CPU
CPU#
Figure 6
Assertion CPU_STP# Waveform Figure
CPU_STP# Functionality Table
CPU_STP#
1
0
CPU#4
Normal
Iref*Mult
CPU
Normal
Float
DRCG
66M
66M
66CLK(0:2)
66Input
66Input
PCI_F/PCI
66Input/2
66Input/2
PCI
USB/DOT
48M
48M
66Input/2
66Input/2
CPU_STP# De-assertion (transition from logic ‘0’ to logic ‘1’)
The de-assertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produces when the
clock resumes. The maximum latency from the de-assertion to active outputs is no more than 2 CPU clock cycles.
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