參數(shù)資料
型號: BXM80526B650256
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 64-BIT, 650 MHz, MICROPROCESSOR, CPGA495
封裝: MICRO PGA-495
文件頁數(shù): 72/84頁
文件大?。?/td> 450K
代理商: BXM80526B650256
Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet
Intel Corporation
66
inactive at any time, but clocks and power must again be stable before the rising edge of
PWRGOOD. It must also meet the minimum pulse width specified in Table 17 (Section 3.7) and
be followed by a 1 ms RESET# pulse.
Figure 26. PWRGOOD Relationship at Power On
BCLK
PWRGOOD
RESET#
D0026-01
1 msec
V
IH25,min
V
CC
,
V
CCT
,
V
REF
The PWRGOOD signal, which must be supplied to the processor, is used to protect internal
circuits against voltage sequencing issues. The PWRGOOD signal should be driven high
throughout boundary scan operation.
REQ[4:0]# (I/O - GTL+)
The REQ[4:0]# (Request Command) signals must be connected to the appropriate pins/balls on
both agents on the system bus. They are asserted by the current bus owner when it drives A[35:3]#
to define the currently active transaction type.
RESET# (I - GTL+)
Asserting the RESET# signal resets the processor to a known state and invalidates the L1 and L2
caches without writing back Modified (M state) lines. For a power-on type reset, RESET# must
stay active for at least 1 msec after VCC and BCLK have reached their proper DC and AC
specifications and after PWRGOOD has been asserted. When observing active RESET#, all bus
agents will deassert their outputs within two clocks. RESET# is the only GTL+ signal that does
not have on-die GTL+ termination. A 56.2
1% terminating resistor connected to VCCT is
required.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for the power-
on configuration. The configuration options are described in Section 4 and in the Pentium
II
Processor Developer’s Manual.
Unless its outputs are tri-stated during power-on configuration, after an active-to-inactive
transition of RESET#, the processor optionally executes its built-in self-test (BIST) and begins
program execution at reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected to the
appropriate pins/balls on both agents on the system bus.
相關(guān)PDF資料
PDF描述
BXM80526B450256 64-BIT, 450 MHz, MICROPROCESSOR, CPGA495
BXM80526B500256 64-BIT, 500 MHz, MICROPROCESSOR, CPGA495
BXM80526B600256 64-BIT, 600 MHz, MICROPROCESSOR, CPGA495
BY8400 Fast high-voltage soft-recovery rectifiers
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