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| 型號： | BXM80526B650256 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 650 MHz, MICROPROCESSOR, CPGA495 |
| 封裝： | MICRO PGA-495 |
| 文件頁數(shù)： | 28/84頁 |
| 文件大?。?/td> | 450K |
| 代理商： | BXM80526B650256 |
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Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet
Intel Corporation
26
Table 21. Quick Start/Deep Sleep AC Specifications
1
TJ = 0°C to 100°C; VCC = 1.35V ±100 mV or 1.60V ±115 mV; V CCT = 1.50V ±115 mV
Symbol Parameter
Min Max Unit
Figure
Notes
T45
Stop Grant Cycle Completion to Clock Stop
100
BCLKs Figure 14
T46
Stop Grant Cycle Completion to Input Signals Stable
0
s
Figure 14
T47
Deep Sleep PLL Lock Latency
0
30
s
Figure 14,
Figure 15
Note 2
T48
STPCLK# Hold Time from PLL Lock
0
ns
Figure 14
T49
Input Signal Hold Time from STPCLK# Deassertion
8
BCLKs Figure 14
NOTES:
1.
Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.
2.
The BCLK Settling Time specification (T60) applies to Deep Sleep state exit under all conditions.
Table 22. Stop Grant/Sleep/Deep Sleep AC Specifications
TJ = 0°C to 100°C; VCC = 1.35V ±100 mV or 1.60V ±115 mV; V CCT = 1.50V ±115 mV
Symbol
Parameter
Min Max Unit
Figure
T50
SLP# Signal Hold Time from Stop Grant Cycle Completion 100
BCLKs
Figure 15
T51
SLP# Assertion to Input Signals Stable
0
ns
Figure 15
T52
SLP# Assertion to Clock Stop
10
BCLKs
Figure 15
T54
SLP# Hold Time from PLL Lock
0
ns
Figure 15
T55
STPCLK# Hold Time from SLP# Deassertion
10
BCLKs
Figure 15
T56
Input Signal Hold Time from SLP# Deassertion
10
BCLKs
Figure 15
NOTE:
Input signals other than RESET# must be held constant in the Sleep state. The BCLK Settling Time specification
(T60) applies to Deep Sleep state exit under all conditions.
Table 23. Intel SpeedStep Technology AC Specifications
TJ = 0°C to 100°C; VCC = 1.35V ±100 mV or 1.6V ±115 mV; V CCT = 1.5V ±115 mV
Symbol
Parameter
Min
Max
Unit Figure
Notes
T57
GHI# Setup Time from BCLK Restart
150
ns
Figure 16 Note 1
T58
GHI# Hold Time from BCLK Restart
30
s
Figure 16 Note 1
T59
GHI# Sample Delay
10
s
Figure 16 Note 1
T60
BCLK Settling Time
150
ns
Figure 16 Notes 2, 3
NOTES:
1.
GHI# is ignored until 10
s after BCLK stops, the setup and hold window must occur after this time.
2.
BCLK must meet the BCLK AC specification from Table 14 within 150 ns of turning on (rising above VIL,BCLK).
3.
This specification applies to the exit from the Deep Sleep state whether or not a Intel SpeedStep technology operating
mode transition occurs.
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