參數(shù)資料
型號(hào)： BXM80526B650256
廠商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 64-BIT, 650 MHz, MICROPROCESSOR, CPGA495
封裝： MICRO PGA-495
文件頁(yè)數(shù)： 65/84頁(yè)
文件大小： 450K
代理商： BXM80526B650256
Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet
Intel Corporation
60
BCLK (I - 2.5V Tolerant)
The BCLK (Bus Clock) signal determines the system bus frequency. Both system bus agents must
receive this signal to drive their outputs and latch their inputs on the BCLK rising edge. All
external timing parameters are specified with respect to the BCLK signal.
BERR# (I/O - GTL+)
The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus
protocol violation. It may be driven by either system bus agent and must be connected to the
appropriate pins/balls of both agents, if used. However, the mobile Pentium III processors do not
observe assertions of the BERR# signal.
BERR# assertion conditions are defined by the system configuration. Configuration options
enable the BERR# driver as follows:
Enabled or disabled
Asserted optionally for internal errors along with IERR#
Asserted optionally by the request initiator of a bus transaction after it observes an error
Asserted by any bus agent when it observes an error in a bus transaction
BINIT# (I/O - GTL+)
The BINIT# (Bus Initialization) signal may be observed and driven by both system bus agents and
must be connected to the appropriate pins/balls of both agents, if used. If the BINIT# driver is
enabled during the power-on configuration, BINIT# is asserted to signal any bus condition that
prevents reliable future information.
If BINIT# is enabled during power-on configuration, and BINIT# is sampled asserted, all bus state
machines are reset and any data which was in transit is lost. All agents reset their rotating ID for
bus arbitration to the state after reset, and internal count information is lost. The L1 and L2 caches
are not affected.
If BINIT# is disabled during power-on configuration, a central agent may handle an assertion of
BINIT# as appropriate to the Machine Check Architecture (MCA) of the system.
BNR# (I/O - GTL+)
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent that is unable
to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new
transactions.
Since multiple agents may need to request a bus stall simultaneously, BNR# is a wired-OR signal
that must be connected to the appropriate pins/balls of both agents on the system bus. In order to
avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers,
BNR# is activated on specific clock edges and sampled on specific clock edges.
相關(guān)PDF資料
PDF描述
BXM80526B450256 64-BIT, 450 MHz, MICROPROCESSOR, CPGA495
BXM80526B500256 64-BIT, 500 MHz, MICROPROCESSOR, CPGA495
BXM80526B600256 64-BIT, 600 MHz, MICROPROCESSOR, CPGA495
BY8400 Fast high-voltage soft-recovery rectifiers
BY8404 Fast high-voltage soft-recovery rectifiers
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