參數(shù)資料
型號(hào)： BXM80526B650256
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 650 MHz, MICROPROCESSOR, CPGA495
封裝： MICRO PGA-495
文件頁(yè)數(shù)： 63/84頁(yè)
文件大小： 450K
代理商： BXM80526B650256
Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet
Intel Corporation
58
7.0
Processor Initialization and Configuration
7.1
Description
The mobile Pentium III processor has some configuration options that are determined by hardware
and some that are determined by software. The processor samples its hardware configuration at
reset on the active-to-inactive transition of RESET#. Most of the configuration options for the
mobile Pentium III processor are identical to those of the Pentium II processor. The Pentium
II
Processor Developer’s Manual describes these configuration options. New configuration options
for the mobile Pentium III processor are described in the remainder of this section.
7.1.1
Quick Start Enable
The processor normally enters the Stop Grant state when the STPCLK# signal is asserted but it
will enter the Quick Start state instead if A15# is sampled active on the RESET# signal’s active-
to-inactive transition. The Quick Start state supports snoops from the bus priority device like the
Stop Grant state but it does not support symmetric master snoops nor is the latching of interrupts
supported. A “1” in bit position 5 of the Power-on Configuration register indicates that the Quick
Start state has been enabled.
7.1.2
System Bus Frequency
The current generation mobile Pentium III processor will only function with a system bus
frequency of 100 MHz. Bit positions 18 to 19 of the Power-on Configuration register indicates at
which speed a processor will run. A “00” in bits [19:18] indicates a 66-MHz bus frequency, a “10”
indicates a 100-MHz bus frequency, and a “01” indicates a 133-MHz bus frequency.
7.1.3
APIC Enable
If the PICD0 signal is sampled low on the active-to-inactive transition of the RESET# signal then
the PICCLK signal can be tied to VSS. Otherwise the PICD[1:0] signals must be pulled up to VCCT
and PICCLK must be supplied. Driving PICD0 low at reset also has the effect of clearing the
APIC Global Enable bit in the APIC Base MSR. This bit is normally set when the processor is
reset, but when it is cleared the APIC is completely disabled until the next reset.
7.2
Clock Frequencies and Ratios
The mobile Pentium III processor uses a clock design in which the bus clock is multiplied by a
ratio to produce the processor’s internal (or “core”) clock. Unlike some of the mobile Pentium II
processors, the ratio used is programmed into the processor during manufacturing. The bus ratio
programmed into the processor is visible in bit positions 22 to 25 of the Power-on Configuration
register. Table 15 shows the 4-bit codes in the Power-on Configuration register and their
corresponding bus ratios.
相關(guān)PDF資料
PDF描述
BXM80526B450256 64-BIT, 450 MHz, MICROPROCESSOR, CPGA495
BXM80526B500256 64-BIT, 500 MHz, MICROPROCESSOR, CPGA495
BXM80526B600256 64-BIT, 600 MHz, MICROPROCESSOR, CPGA495
BY8400 Fast high-voltage soft-recovery rectifiers
BY8404 Fast high-voltage soft-recovery rectifiers
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