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參數(shù)資料
| 型號： | BX805499040 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 1600 MHz, MICROPROCESSOR, CPGA611 |
| 封裝： | PGA-611 |
| 文件頁數(shù)： | 5/108頁 |
| 文件大小： | 2315K |
| 代理商： | BX805499040 |
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102
Dual-Core Intel Itanium Processor 9000 Series Datasheet
Signals Reference
A.1.51
RESET# (I)
Asserting the RESET# signal resets all processors to known states and invalidates all
caches without writing back Modified (M state) lines. RESET# must remain asserted for
one millisecond for a “warm” reset; for a power-on reset, RESET# must stay asserted
for at least one millisecond after PWRGOOD and BCLKp have reached their proper
specifications. On observing asserted RESET#, all system bus agents must deassert
their outputs within two clocks.
A number of bus signals are sampled at the asserted-to-deasserted transition of
RESET# for the power-on configuration.
Unless its outputs are tristated during power-on configuration, after asserted-to-
deasserted transition of RESET#, the processor begins program execution at the reset-
vector
A.1.52
RP# (I/O)
The Request Parity (RP#) signal is driven by the requesting agent, and provides parity
protection for ADS# and REQ[5:0]#.
A correct parity signal is high if an even number of covered signals are low and low if an
odd number of covered signals are low. This definition allows parity to be high when all
covered signals are high.
Table A-10. Transaction Types Defined by REQa#/REQb# Signals
Transaction
REQa[5:0]#
REQb[5:0]#
5
432
1
0
543
210
Deferred Reply
0000
0
x
Reserved
0000
0
1
0
x
Interrupt
Acknowledge
0010
0
DSZ[1:0]#
000
Special
Transactions
0010
0
DSZ[1:0]#
001
Reserved
0010
0
DSZ[1:0]#
01
x
Reserved
0010
0
1
0
DSZ[1:0]#
0
x
Interrupt
0010
0
1
0
DSZ[1:0]#
100
Purge TC
0010
0
1
0
DSZ[1:0]#
101
Reserved
0010
0
1
0
DSZ[1:0]#
11
x
I/O Read
0100
0
DSZ[1:0]#
x
I/O Write
0100
0
1
0
DSZ[1:0]#
x
Reserved
0110
0
x
0
DSZ[1:0]#
x
Memory Read &
Invalidate
0
ASZ[1:0]#
0
1
0
DSZ[1:0]#
LEN[2:0]#
Reserved
0
ASZ[1:0]#
0
1
0
DSZ[1:0]#
LEN[2:0]#
Memory Read
0
ASZ[1:0]#
1
D/C#
0
DSZ[1:0]#
LEN[2:0]#
Memory Read
Current
1
ASZ[1:0]#
1
0
DSZ[1:0]#
LEN[2:0]#
Reserved
1
ASZ[1:0]#
1
0
DSZ[1:0]#
LEN[2:0]#
Memory Write
0
ASZ[1:0]#
1
WSNP#
1
0
DSZ[1:0]#
LEN[2:0]#
Cache Line
Replacement
1
ASZ[1:0]#
1
WSNP#
1
0
DSZ[1:0]#
0
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