參數(shù)資料
型號(hào)： BX80532PG3000D
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 3000 MHz, MICROPROCESSOR, XGA478
封裝： BOXED PROCESSOR
文件頁(yè)數(shù)： 71/88頁(yè)
文件大小： 1502K
代理商： BX80532PG3000D
Intel Pentium 4 Processor on 0.13 Micron Process Datasheet
73
Features
6.2.3
Stop-Grant State—State 3
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle.
Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven
(allowing the level to return to VCC) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the system bus should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched
and can be serviced by software upon exit from the Stop-Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the
STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should
only be de-asserted one or more bus clocks after the de-assertion of SLP#.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
system bus (see Section 6.2.4). A transition to the Sleep state (see Section 6.2.5) will occur with the
assertion of the SLP# signal.
While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal State. Only one occurrence
of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process snoops on the system bus and it will latch
interrupts delivered on the system bus.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if
there is any pending interrupt latched within the processor. Pending interrupts that are blocked by
the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to
system logic that it should return the processor to the Normal state.
6.2.4
HALT/Grant Snoop State—State 4
The processor will respond to snoop or interrupt transactions on the system bus while in Stop-Grant
state or in AutoHALT Power Down state. During a snoop or interrupt transaction, the processor
enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the
system bus has been serviced (whether by the processor or other agent on the system bus) or the
interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will
return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BX80532PG3200D 制造商:Intel 功能描述:MPU PENTIUM 4 NETBURST 64-BIT 0.13UM 3.2GHZ - Boxed Product (Development Kits)
BX80532PG3200F 制造商:Intel 功能描述:MPU PENTIUM 4 NETBURST 64-BIT 0.13UM 3.2GHZ - Boxed Product (Development Kits)
BX80532PG3400F 制造商:Intel 功能描述:MPU PENTIUM 4 PROCESSOR 64-BIT 0.13UM 3.4GHZ 775-PIN FCLGA4 - Boxed Product (Development Kits)
BX80532RC2000B 制造商:Intel 功能描述:MPU CELERON PROCESSOR 0.13UM 2GHZ - Boxed Product (Development Kits)
BX80532RC2100B 制造商:Intel 功能描述:MPU CELERON PROCESSOR 0.13UM 2.1GHZ 478-PIN FCPGA2 - Boxed Product (Development Kits)
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