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參數(shù)資料
| 型號： | BX80532PG3000D |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 3000 MHz, MICROPROCESSOR, XGA478 |
| 封裝： | BOXED PROCESSOR |
| 文件頁數(shù)： | 13/88頁 |
| 文件大?。?/td> | 1502K |
| 代理商： | BX80532PG3000D |
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20
Intel Pentium 4 Processor on 0.13 Micron Process Datasheet
Electrical Specifications
2.5
Reserved, Unused Pins, and TESTHI[12:0]
All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or to any
other signal (including each other) can result in component malfunction or incompatibility with
future Pentium 4 processors on 0.13 micron process. See Chapter 4 for a pin listing of the processor
and the location of all RESERVED pins.
For reliable operation, always connect unused inputs or bidirectional signals that are not terminated
on the die to an appropriate signal level. Note that on-die termination has been included on the
Pentium 4 processor on 0.13 micron process to allow signals to be terminated within the processor
silicon. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is
provided on the processor silicon. Table 2-3 lists details on AGTL+ signals that do not include on-
die termination. Unused active high inputs should be connected through a resistor to ground (VSS).
Refer to the appropriate platform design guide for the appropriate resistor values.
Unused outputs can be left unconnected. However, this may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying
bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. For unused AGTL+ input or I/O signals that don’t have on-die
termination, use pull-up resistors of the same value in place of the on-die termination resistors
(RTT). See Table 2-14.
The TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and used outputs must be terminated on the system board. Unused outputs may
be terminated on the system board or left unconnected. Note that leaving unused output
unterminated may interfere with some TAP functions, complicate debug probing, and prevent
boundary scan testing. Signal termination for these signal types is discussed in the appropriate
platform design guide listed in Table 1-1.
The TESTHI pins should be tied to the processor VCC using a matched resistor, where a matched
resistor has a resistance value within ± 20% of the impedance of the board transmission line traces.
For example, if the trace impedance is 50
, then a value between 40 and 60 is required.
The TESTHI pins may use individual pull-up resistors or may be grouped together as follows:
1. TESTHI[1:0]
2. TESTHI[5:2]
3. TESTHI[10:8]
4. TESTHI[12:11]
A matched resistor should be used for each group.
Additionally, if the ITPCLKOUT[1:0] pins are not used, they may be connected individually to
VCC using matched resistors or may be grouped with TESTHI[5:2] with a single matched resistor.
If they are being used, individual termination with 1 k
resistors is required. Tying
ITPCLKOUT[1:0] directly to VCC or sharing a pull-up resistor to VCC will prevent use of debug
interposers. This implementation is strongly discouraged for system boards that do not implement
an inboard debug port.
As an alternative, group2 (TESTHI[5:2]) and the ITPCLKOUT[1:0] pins may be tied directly to
the processor VCC. This has no impact on system functionality. TESTHI0 and TESTHI12 may also
be tied directly to the processor VCC if resistor termination is a problem, but matched resistor
termination is recommended. In the case of the ITPCLKOUT[1:0] pins, direct tie to VCC is
strongly discouraged for system boards that do not implement an inboard debug port.
Tying any of the TESTHI pins together will prevent the ability to perform boundary scan testing.
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