參數(shù)資料
型號(hào)： BX80532PC2200D
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 2200 MHz, MICROPROCESSOR, XMA
封裝： BOXED PROCESSOR
文件頁(yè)數(shù)： 58/88頁(yè)
文件大小： 1502K
代理商： BX80532PC2200D
Intel Pentium 4 Processor on 0.13 Micron Process Datasheet
61
Pin Lists and Signal Descriptions
DRDY#
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of all processor system bus agents.
DSTBN[3:0]#
Input/
Output
Data strobe used to latch in D[63:0]#:
DSTBP[3:0]#
Input/
Output
Data strobe used to latch in D[63:0]#:
FERR#/PBE#
Output
FERR#/PBE# (floating point error/pending break event) is a multiplexed signal
which is qualified by STPCLK#. When STPCLK# is not asserted, FERR#
indicates a floating-point error and will be asserted when the processor detects
an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE#
is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for
compatibility with systems using Microsoft MS-DOS*-type floating-point error
reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates
that the processor has a pending break event waiting for service. The assertion
of FERR#/PBE# indicates that the processor should be returned to the Normal
state. When FERR#/PBE# is asserted, indicating a break event, it will remain
asserted until STPCLK# is deasserted. For addition information on the pending
break event functionality, including the identification of support of the feature and
enable/disable information, refer to the IA-32 Intel Architecture Software
Developer’s Manual (Vol. 1 - Vol. 3)
and the Intel Processor Identification and
the CPUID Instruction
application note.
GTLREF
Input
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set at 2/3 V
CC. GTLREF is used by the AGTL+ receivers to determine if
a signal is a logical 0 or logical 1. Refer to the appropriate Platform Design Guide
for more information.
HIT#
HITM#
Input/
Output
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Any system bus agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be continued by reasserting
HIT# and HITM# together.
IERR#
Output
IERR# (Internal Error) is asserted by a processor as the result of an internal
error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction
on the processor system bus. This transaction may optionally be converted to an
external error signal (e.g., NMI) by system core logic. The processor will keep
IERR# asserted until the assertion of RESET#.
This signal does not have on-die termination and must be terminated on the
system board.
Table 4-3. Signal Descriptions (Sheet 4 of 8)
Name
Type
Description
Signals
Associated Strobe
D[15:0]#, DBI0#
DSTBN0#
D[31:16]#, DBI1#
DSTBN1#
D[47:32]#, DBI2#
DSTBN2#
D[63:48]#, DBI3#
DSTBN3#
Signals
Associated Strobe
D[15:0]#, DBI0#
DSTBP0#
D[31:16]#, DBI1#
DSTBP1#
D[47:32]#, DBI2#
DSTBP2#
D[63:48]#, DBI3#
DSTBP3#
相關(guān)PDF資料
PDF描述
BU-61588F0-100W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61588F3-482L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61588F3-592S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BX80532PC2400D 制造商:Intel 功能描述:MPU PENTIUM 4 NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits)
BX80532PC2500D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
BX80532PC2600D 制造商:Intel 功能描述:P4 Socket 478 2.6GHz with Fan
BX80532PE2266D 制造商:Intel 功能描述:MPU PENTIUM 4 PROCESSOR NETBURST 64-BIT 0.13UM 2.26GHZ 478- - Boxed Product (Development Kits)
BX80532PE2400D 制造商:Intel 功能描述:MPU PENTIUM 4 NETBURST 64-BIT 0.13UM 2.4GHZ 478-PIN FCPGA2 - Boxed Product (Development Kits)
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