參數(shù)資料
型號(hào)： BX80532PC2200D
廠(chǎng)商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 2200 MHz, MICROPROCESSOR, XMA
封裝： BOXED PROCESSOR
文件頁(yè)數(shù)： 54/88頁(yè)
文件大?。?/td> 1502K
代理商： BX80532PC2200D
58
Intel Pentium 4 Processor on 0.13 Micron Process Datasheet
Pin Lists and Signal Descriptions
4.2
Signal Descriptions
Table 4-3. Signal Descriptions (Sheet 1 of 8)
Name
Type
Description
A[35:3]#
Input/
Output
A[35:3]# (Address) define a 236-byte physical memory address space. In
sub-phase 1 of the address phase, these pins transmit the address of a
transaction. In sub-phase 2, these pins transmit transaction type information.
These signals must connect the appropriate pins of all agents on the Intel
Pentium 4 processor on 0.13 micron process system bus. A[35:3]# are
protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals
and are latched into the receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor samples a subset
of the A[35:3]# pins to determine power-on configuration. See Section 6.1 for
more details.
A20M#
Input
If A20M# (Address-20 Mask) is asserted, the processor masks physical address
bit 20 (A20#) before looking up a line in any internal cache and before driving a
read/write transaction on the bus. Asserting A20M# emulates the 8086
processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M#
is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
ADS#
Input/
Output
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new
transaction.
ADSTB[1:0]#
Input/
Output
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and
falling edges. Strobes are associated with signals as shown below.
AP[1:0]#
Input/
Output
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,
A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is
high if an even number of covered signals are low and low if an odd number of
covered signals are low. This allows parity to be high when all the covered
signals are high. AP[1:0]# should connect the appropriate pins of all Pentium 4
processors on 0.13 micron process system bus agents. The following table
defines the coverage model of these signals.
BCLK[1:0]
Input
The differential pair BCLK (Bus Clock) determines the system bus frequency. All
processor system bus agents must receive these signals to drive their outputs
and latch their inputs.
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing VCROSS.
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
ADSTB0#
A[35:17]#
ADSTB1#
Request Signals
Subphase 1
Subphase 2
A[35:24]#
AP0#
AP1#
A[23:3]#
AP1#
AP0#
REQ[4:0]#
AP1#
AP0#
相關(guān)PDF資料
PDF描述
BU-61588F0-100W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61588F3-482L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61588F3-592S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61588G0-200Z 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61588G0-500 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BX80532PC2400D 制造商:Intel 功能描述:MPU PENTIUM 4 NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits)
BX80532PC2500D 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Microprocessor
BX80532PC2600D 制造商:Intel 功能描述:P4 Socket 478 2.6GHz with Fan
BX80532PE2266D 制造商:Intel 功能描述:MPU PENTIUM 4 PROCESSOR NETBURST 64-BIT 0.13UM 2.26GHZ 478- - Boxed Product (Development Kits)
BX80532PE2400D 制造商:Intel 功能描述:MPU PENTIUM 4 NETBURST 64-BIT 0.13UM 2.4GHZ 478-PIN FCPGA2 - Boxed Product (Development Kits)
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