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參數(shù)資料
| 型號： | BUS-65164-180K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| 封裝： | 1.900 X 1 INCH, 0.215 INCH HEIGHT, FP-70 |
| 文件頁數(shù)： | 5/40頁 |
| 文件大?。?/td> | 349K |
| 代理商： | BUS-65164-180K |
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FIGURE 4. RT TO BC (TRANSMIT) TIMING (CONTINUED)
1.350
0.910
1.470
1.010
1.260
0.880
1.365
0.965
1.405
60
0.920
100
1.795
1.430
2.085
s
MID-PARTIY CROSSING OF LAST DATA WORD TO INCMD RISING
t18(@16MHz)
s
MID-PARTIY CROSSING OF LAST DATA WORD TO INCMD RISING
18(@12MHz)
s
MID-SYNC CROSSING OF LAST DATA WORD TO WRT FALLING
t17(@16MHz)
s
MID-SYNC CROSSING OF LAST DATA WORD TO WRT FALLING
t17(@12MHz)
ms
ns
MID-SYNC CROSSING OF STATUS RESPONSE TO WRT RISING
END OF DATA TRANSFER CYLE TO VALID NEXT WC (Note 3)
t14(@12MHz)
t16
ns
s
t13
t15(@16MHz)
s
t15(@12MHz)
s
MID-SYNC CROSSING OF STATUS RESPONSE TO WRT RISING
t14(@16MHz)
UNITS
TYP
DESCRIPTION
1.700
1.305
0.840
MAX
MIN
MID-SYNC CROSSING OF TRANSMITTED DATA TO START OF DATA TRANSFER CYCLE (Note 2)
MID-SYNC CROSSING OF STATUS RESPONSE TO RTFAIL RISING
Notes:
1)IF ADDR_ENA IS LOGIC “1”, CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED
(DT_ACK = LOGIC “0”).
2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCES t6 AND t15 ARE DEFINED AS THE FALLING EDGE OF
DT_REQ.
3)THE TRAILING EDGE OF REFERENCE t9 AND THE LEADING EDGE OF TIME REFERENCE t16 ARE DEFINED AS THE RISING EDGE OF DT_REQ.
4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES.
5)IF THE COMMAND WORD TRANSFER CYCLE IS NOT COMPLETE (i.e., DT_REQ IS STILL LOGIC LOW) BY THE TIME INDICATED BY THE TRAILING EDGE OF
t11, A6 WILL BE HELD LOW UNTIL THE AFTER TRANSFER CYCLE IS COMPLETE (60 ns MAX AFTER THE RISING EDGE OF DT_REQ).
MID-SYNC CROSSING OF TRANSMITTED DATA TO START OF DATA TRANSFER CYCLE (Note 2)
MID-PARITY
DATA
MID-SYNC
DATA
MID-SYNC
STATUS
MID-SYNC
COMMAND
t18
t9
t17
CWC=2
t16
CWC=1
t9
t15
t16
CWC=0
t14
t15
t13
SYMBOL
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