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| 型號： | BUS-65164-180K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| 封裝： | 1.900 X 1 INCH, 0.215 INCH HEIGHT, FP-70 |
| 文件頁數(shù)： | 24/40頁 |
| 文件大?。?/td> | 349K |
| 代理商： | BUS-65164-180K |
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SIMPLE SYSTEM INTERFACE
FIGURE 16 illustrates the capability of the STIC to operate in a
system with no host processor. A simple linear addressing
scheme is used that can be easily decoded to form read and
write signals for direct access to data buffers or data latches. A
double buffered mechanism may be used on received data in
order to maintain data validity and consistency.
The latched discrete outputs section of the drawing uses two
sets of latches. The first latch is updated when the received data
word is transferred from the STIC. The second latch is not updat-
ed until the message is validated, as indicated by the signal
Good Block Received (GBR). If an error, such as parity or
Manchester, occurs on a received data word, all the data asso-
ciated with that message will be ignored, thus fulfilling the data
validity/consistancy requirement.
DMA INTERFACE
The STIC may be interfaced to a host processor by means of a
simple DMA interface. The address and control lines may be
placed in a three-state mode by setting the ADDR_ENA signal to
logic “1”. While the STIC is not accessing the RAM (i.e.,
DT_ACK is logic “1”) the address, data, and control lines (CS,
WRT) are held in a high impedance state. The signals CS and
WRT require pull-up resistors.
The STIC may be programmed to operate in either a 16-bit
transfer mode (FIGURE 17) or an 8-bit transfer mode (FIGURE
18). In 16-bit mode (DB_SEL set to logic “0”) the signal A0 is not
used (always logic “1”) and 16-bit transfers are performed on
data lines D0..D15. In 8-bit mode (DB_SEL set to logic “1”) the
signal A0 is used to indicate whether the upper (MSB) data byte
(A0 set to logic “1”) or the lower (LSB) data byte (A0 set to logic
“0”) is being transferred. The upper and lower data bytes are not
multiplexed internally, therefore, the signals must be connected
externally. D0 must be connected to D8, D1 must be connected
to D9, ... , and D7 must be connected to D15
30
FIGURE 16. BUS-65153 MINIMUM COMPLEXITY SYSTEM
Q
LATCH
DQ
D
W0
WRITE
ADDRESS
DECODER
CS
A0..A13
__
WN
Vcc
D
Q
_
Q
LATCHED
DISCRETE
OUTPUTS
Q
LATCH
DQ
D
BUS
65153
"STIC"
Vcc
D
_
Q
TRI-STATE
BUFFER
Q
NBGRT
GBR
_____
___
ADDRESS
DECODER
READ
R0
DISCRETE
BUFFERED
INPUTS
TRI-STATE
BUFFER
RN
DB GRT
DB0..DB15
______
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