參數(shù)資料
型號(hào): BUS-65164-180K
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70
封裝: 1.900 X 1 INCH, 0.215 INCH HEIGHT, FP-70
文件頁數(shù): 15/40頁
文件大?。?/td> 349K
代理商: BUS-65164-180K
22
t2
TRANSMIT COMMAND
RECEIVE COMMAND
MID-PARITY
t1
PREVIOUS COMMAND
PRESENT COMMAND
t3
t4
t5
t8
t11
CWC=0
WC
t6
t7
t9
t10
1553 BUS
_______
NBGRT
_____
ME
__
A6 (COMMAND/DATA)
_______
LMC, A13(BRDCST/OWN ADDRS),
A12(T/R),A11-A7(SA4-SA0)
___
_________
_
A5-A1
(WC/MC4-0, CWC4-0)
INCMD
_____
HS_FAIL
___
DTREQ, DTGRT, DTACK,
_____
__
ILLEGAL, SERVREQ,
SSFLAG, BUSY
______ ____
_______
GBR
______
DATA15-0, CS (NOTE 1)
___
WRT (NOTE 1)
RTFAIL
MIN
MAX
0.97
1.56
0.87
SYMBOL
DESCRIPTION
TYP
UNITS
t1(@12MHz)
COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT
ms
t1(@16MHz)
COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT
ms
t2(@12MHz)
NBGRT PULSE WIDTH
ns
t2(@16MHz)
NBGRT PULSE WIDTH
ns
t3
NBGRT RISING EDGE TO A6 FALLING EDGE
ns
t4(@12MHz)
NBGRT FALLING EDGE TO ADDRESS VALID, LMC
ns
t4(@16MHz)
NBGRT FALLING EDGE TO VALID ADDRESS, LMC
ns
t5(@12MHz)
NBGRT FALLING EDGE TO INCMD FALLING EDGE
ns
t5(@16MHz)
NBGRT FALLING EDGE TO INCMD FALLING EDGE
ns
t6(@12MHz)
NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE
ms
t6(@16MHz)
NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE (Note 2)
ms
t7
NBGRT FALLING EDGE TO VALID STATUS INPUTS
ms
t8
INCMD FALLING EDGE TO CWC VALID
t9
DATA TRANSFER CYCLE TIME (Notes 2,3,4)
1.38
140
190
100
150
45
300
410
220
330
800
865
590
655
1.19
1.28
0.88
0.97
4.1
5
60
FIGURE 9. RT TO RT (RECEIVE) TIMEOUT TIMING
See Note 4
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