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參數(shù)資料
| 型號： | BUS-65164-180K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| 封裝： | 1.900 X 1 INCH, 0.215 INCH HEIGHT, FP-70 |
| 文件頁數(shù)： | 29/40頁 |
| 文件大小： | 349K |
| 代理商： | BUS-65164-180K |
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35
A11 through A07 : Subaddress [4:0] - These outputs are the latched data from the Subaddress field of the
received Command Word. They are updated after NBGRT but before INCMD goes active. They are cleared by
RESET. A11 corresponds to SA4 which is the MSB and A07 corresponds to SA0 which is the LSB. (Note 1)
O
A07 (LSB)
57
O
A00
A08
64
56
O
A01 (LSB)
A09
63
55
O
A02
A10
62
54
TABLE 5. BUS-65153 PIN DESCRIPTIONS - CONTINUED
ADDRESS BUS (14)
DESCRIPTION
Transmit/Receive - Latched output signal that represents the latched T/R bit (bit 10) of the present Command
Word. It is updated after NBGRT but before INCMD goes active. A logic “1” indicates a transmit command, a logic
“0” indicates a receive command. Cleared by RESET. (Note 1)
O
I/O
O
A03
A11 (MSB)
61
53
A04
A12
60
52
A05 (MSB)
A13
59
50
A06
NAME
58
A05 through A01 (LSB):Word Count [4:0] / Current Word Count [4:0]. Multiplexed output signals which are defined
as follows: these outputs are the latched data from the Word Count field of the received Command Word. They
are updated after NBGRT but before INCMD goes active. They are cleared by RESET. For the Command Word
transfer (A06 = 0) of a nonmode code Command Word, A05-A00 will be 00000. For a mode code Command
Word transfer, A05-A00 will reflect the mode code field of the Command Word. If the present command is not a
mode code and INCMD is active then these lines become the output of a current word counter. That is, when
INCMD goes active, these outputs go to logic “0” and are then incremented after every Data Word transfer or
handshake timeout. For a mode code transfer, the single Data Word is accessed at an address location that is
offset by a value of 32 above that of the location for the corresponding Command Word. When INCMD goes inac-
tive, A05-A01 become the latched Word Count field again. A5 corresponds to WC4 which is the MSB and A1 cor-
responds to WC0 which is the LSB. (Note 1)
Transmitter Inhibit. A low level on this input disables both 1553 transmitters.
I
TXINH
49
DESCRIPTION
CLOCK, RESET, AND TRANSMITTER INHIBIT (4)
12 or 16 MHz clock input.
Clock Frequency Select. If high, selects 12 MHz clock input. If low, selects a 16 MHz clock input.
Master Reset - Active low input signal (2 clock cycles minimum) used to reset the entire circuit.
I/O
I
RESET
45
CLOCKSEL
43
CLOCK IN
51
NAME
Notes:
1. A13 through A0, CS, and WRT will be placed in a high impedance state if ADDR_ENA is high and DTACK is inactive (high).
2. The RT Status Word inputs ILLCMD, SERVREQ, SSFLAG, and BUSY are sampled approximately 5 ms following the mid-parity bit zero crossing of the received
Command Word.
PIN NO.
(TABLE 5 CONTINUES ON THE NEXT PAGE.)
Broadcast. Latched output signal that represents the RT Address field of the present Command Word. That is, it
was either a broadcast message (all ones in the RT Address Field) or a command addressed explicitly to this ter-
minal (the address field of the command word matches the terminals's RTADD04 to RTADD0 inputs and RTAD4-
0, RTADP has an odd parity sum.). It is updated after NBGRT but before INCMD goes active. A logic “1” indicates
a broadcast command, a logic “0” indicates a command to the BUS-65153's RT Address. Cleared by RESET.
(Note 1)
Command Word Transfer - Active low level output signal that is asserted when the 1553 Command Word is being
transferred to the subsystem over the parallel data bus. A06 is high during all Data Word transfers. (Note 1)
MSB/LSB - Output signal that is used during 8-bit data transfers to indicate which byte of the present 16-bit word
is being transferred. A logic “1” indicates the upper byte (MSB) and a logic “0” indicates the lower byte (LSB). The
upper byte is transferred first. If a 16-bit data structure is used (DB_SEL = logic “0”), this bit will always be logic
“1” (Note 1)
PIN NO.
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