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| 型號(hào)： | BT865AKPF |
| 英文描述： | Color Encoder Circuit |
| 中文描述： | 顏色編碼器電路 |
| 文件頁(yè)數(shù)： | 37/76頁(yè) |
| 文件大?。?/td> | 1050K |
| 代理商： | BT865AKPF |
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Bt864A/865A
1.0 Circuit Description
YCrCb to NTSC/PAL Digital Video Encoder
1.9 Teletext
100138B
Conexant
1-27
Figure 1-19. Teletext Timing for Bt864A/865A Encoder
NOTE(S):
(1)
Placement of rising edge of TTXREQ is definable using register TXHS[10:0].
(2)
Placement of falling edge of TTXREQ is definable using register TXHE[10:0].
(3)
TTXREQ is generated by the encoder using programmable registers TXHS and TXHE. This allows the user to adjust for the
propagation delay (t
PD
) in CLK cycles of the teletext data source.
(4)
TTXDAT is supplied to the encoder at the proper time to be interpolated by the encoder (t
TTXINT
) and inserted into the video
output signals. The Teletext data must follow the correct protocol. See
“
Teletext
”
on page 1-26.
(5)
t
TTXOWS
is the start of the teletext output window and is fixed internally by the encoder at 10.2 μsec.
(6)
Luma Delay is set to zero.
(7)
t
TTXIWS
is the start of the teletext input window and is fixed internally.
(8)
If the falling edge of TTXREQ does not occur by the end of a video line, the beginning of a new line will automatically reset
TTXREQ.
(9)
2 clock (CLK) counts = 1 pixel clock count.
10.TXE is enabled and video line is a valid teletext line. See
“
Teletext
”
on page 1-26.
TTXREQ
TTXDAT
CVBS/B
(6)
CVBS/G
Y/CVBS
t
PD
(3)
t
TTXINT
(4)
t
TTXOWS
(5)
Internal
Horizontal
Reset
t
TTXIWS
(7)
. . .
. . .
2 3
5 . . .
4
(8)
2 3
5 . . .
4
Internal
Clock (CLK)
Counter
(1)
(2)
Table 1-5. Legal Values to TXHS and TXHE
Pixel rate
TXHS
TXHE
Min. Value
13.5 MHz
2
TXHS + 2
Max. Value
13.5 MHz
0X6BE
0X7FF
Min. Value
14.75 MHz
2
TXHS + 2
Max. Value
14.75 MHz
0X75E
0X7FF
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