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參數(shù)資料
| 型號： | BT865AKPF |
| 英文描述： | Color Encoder Circuit |
| 中文描述： | 顏色編碼器電路 |
| 文件頁數(shù)： | 31/76頁 |
| 文件大?。?/td> | 1050K |
| 代理商： | BT865AKPF |
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Bt864A/865A
1.0 Circuit Description
YCrCb to NTSC/PAL Digital Video Encoder
1.5 Video Timing
100138B
Conexant
1-21
1.5.10 Subcarrier Phasing
In order to maintain correct SC-H phasing, the subcarrier phase is set to zero on
the falling edge of HSYNC* associated with VSYNC* every four (NTSC) or
eight (PAL) fields, unless the SCRESET bit is set to a logical one.
In slave mode, falling HSYNC* may lag falling VSYNC* by 1/4 scan line but
cannot precede falling VSYNC* by more than seven CLK periods for correct
SC-H reset.
Setting SCRESET to one may be useful in situations where the ratio of CLK/2
to HSYNC* edges in a color frame is noninteger, which could produce a
significant phase impulse by resetting to zero.
1.5.11 Vertical Blanking Intervals
For interlaced NTSC/PAL
–
M, if EVBI = 0, scan lines 1
–
21 and 263
–
284,
inclusive, are always blanked regardless of the BLANK* input (SMPTE line
numbering convention).
For interlaced PAL
–
B, D, G, H, I, N, Nc, if EVBI = 0, scan lines 1
–
23,
311
–
335, and 624
–
625, inclusive, are always blanked regardless of the BLANK*
input.
For noninterlaced NTSC/PAL
–
M, if EVBI = 0, scan lines 1
–
17 and 261
–
262,
inclusive, are always blanked regardless of the BLANK* input. For noninterlaced
PAL
–
B, D, G, H, I, N, Nc, if EVBI = 0, scan lines 1
–
22 and 311
–
312, inclusive,
are always blanked regardless of the BLANK* input.
Alternately, all displayed lines in the vertical blanking interval (10
–
21 and
273
–
284 for interlaced NTSC/PAL
–
M; 6
–
23 and 320
–
335 for interlaced PAL
–
B,
D, G, H, I, N, Nc; 10
–
21 for noninterlaced NTSC/PAL
–
M, 7
–
23 for noninterlaced
PAL
–
B, D, G, H, I, N, Nc) may be enabled by setting the EVBI bit to a logical one
(except for caption lines controlled by bits ECCF1 or ECCF2, or the Macrovision
process).
1.5.12 BLANK* Pin
The BLANK* pin can be used to BLANK any portion of the active display lines
(including those enabled by EVBI) by driving the pin to a logical zero.
1.5.13 Noninterlaced Operation
When the Bt864A/865A is programmed for noninterlaced master mode, the
Bt864A/865A always displays FIELD 1, meaning that the falling edges of
HSYNC* and VSYNC* will be output coincidentally. FIELD will be held low if
FIELDI = 0. Additionally, a 30 Hz offset will be subtracted from the color
subcarrier frequency while in NTSC mode so that the color subcarrier phase will
be inverted from field to field.
Transition from interlaced to noninterlaced in master mode, occurs during
FIELD 1 to prevent synchronization disturbance. In slave mode, transition occurs
after a subsequent falling edge of VSYNC*.
NOTE:
Consumer VCRs can record noninterlaced video with minor noise
artifacts, but special effects (e.g., scan > 2x) may not function properly.
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| BT867KPF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Encoder Circuit |
| BT867KPJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Encoder Circuit |
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