
MOTOROLA
D-16
CAN PROTOCOL
Rev. 3
THE MOTOROLA SCALEABLE CAN (MSCAN12)
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D
D.8
Timer Link
The MSCAN12 will generate a timer signal whenever a valid frame has been received. Because
the CAN specification defines a frame to be valid if no errors occurred before the EOF field has
been transmitted successfully, the timer signal will be generated right after the EOF. A pulse of one
bit time is generated. As the MSCAN12 receiver engine also receives the frames being sent by
itself, a timer signal will also be generated after a successful transmission.
The previously described timer signal can be routed into the on-chip Timer Interface Module (TIM
/ ECT). This signal is connected to the Timer n Channel m input
under the control of the Timer
Link Enable (TLNKEN) bit in CMCR0.
After Timer n has been programmed to capture rising edge events it can be used under software
control to generate 16-bit time stamps which can be stored with the received message.
D.9
Clock System
Figure D-7
shows the structure of the MSCAN12 clock generation circuitry. With this flexible
clocking scheme the MSCAN12 is able to handle CAN bus rates ranging from 10 kbps up to 1
Mbps.
The Clock Source bit (CLKSRC) in the MSCAN12 Module Control Register (CMCR1) (see
Section D.12.4
) defines whether the MSCAN12 is connected to the output of the crystal oscillator
(EXTALi) or to a clock twice as fast as the system clock (ECLK).
The clock source has to be chosen such that the tight oscillator tolerance requirements (up to
0.4%) of the CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 50% duty cycle
of the clock is required.
For microcontrollers without the CGM module, CGMCANCLK is driven from the crystal oscillator
(EXTALi).
The timer channel being used for the timer link is integration dependent.
F
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Freescale Semiconductor, Inc.