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參數(shù)資料
| 型號(hào)： | BBT3420-SN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 37/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX QUAD MULTI-RATE 289-EBGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | XAUI，XGMII，MDC/MDIO |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 289-BGA |
| 供應(yīng)商設(shè)備封裝： | 289-BGA（19x19） |
| 包裝： | 托盤 |
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8
3.8 Receive FIFO
The Receive FIFO performs two functions:
1. Channel Alignment
2. Clock Compensation
3.8.1 CHANNEL ALIGNMENT (DESKEW)
Trunking, also known as deskewing, means the alignment of
packet data across multiple channels. 8 byte of RXFIFO is
dedicated for channel alignment.
During high-speed transmission, different active and passive
elements in the links may impart varying delays in the four
channels. In trunking mode, multiple channels share the
same clock (local reference or recovered clock A), which is
used for outputting data on the parallel bus.
As defined by IEEE 802.3ae-2002, packets must start on
channel A (equivalent to Lane 0 in the IEEE 802.3ae-2002
specification). Deskewing is accomplished by monitoring the
contents of the FIFOs to detect the boundary between IDLE
sequences and any non-IDLE data (including data and the
/S/ code), which defines the beginning of the packet, or the
presence of the IEEE 802.3ae-defined /A/ character, for
channel alignment (controlled by MDIO Register 19’h in
Clause 22 format and/or C000’h in Clause 45 format, see
Table 3-24 and/or Table 3-32). When this alignment data is
detected in all four channels, the trunking channel-alignment
operation is performed, and will be held until another such
transition or /A/ character is detected again on any channel.
To maintain channel alignment, such transitions or /A/
characters should occur on all four channels simultaneously
(i.e. within the span of the FIFO). During channel
realignment, up to four code groups may be deleted,
repeated or garbled on any channel.
The deskew state machine is enabled by setting the
DSKW_SM_EN bit (Clause 22 Address 1D’h see Table 3-28;
Clause 45 Address C000’h see Table 3-32) to 1. The
deskew algorithm is implemented according to IEEE spec.
802.3ae. Note that when DSKW_SM_EN is set to 1, the
CAL_EN bit (Clause 22 Address 19’h see Table 3-24;
Clause 45 Address C000’h see Table 3-32) is ignored. When
TABLE 3-3. VALID 10b/8b DECODER PATTERNS
RECEIVING SERDES
NOTES
DESCRIPTION
SERIAL CODE,
CHARACTER
TRANS_EN
BIT (Note 2)
E-BIT
K-BIT
RD DATA
Valid Data
X
0
0-FF’h
Same Data Value as Transmitted
/K/ (Sync) K28.5
1
0
1
= XGMII IDLE (Note 3)
Default 107’h
0
1
BC
Comma (Note 1)
/A/ (Align) K28.3
1
0
1
= XGMII IDLE (Note 3)
Default 107’h
0
1
7C
Align (Note 1)
/R/ (Skip) K28.0
1
0
1
= XGMII IDLE (Note 3)
Default 107’h
0
1
1C
Alternate Idle (Note 1)
/S/ K27.7
X
0
1
FB
Start
/T/ K29.7
X
0
1
FD
Terminate
K28.1
X
0
1
3C
Extra comma
/F/ K28.2
X
0
1
5C
Signal Ordered_Set marker
/Q/ K28.4
X
0
1
9C
Sequence Ordered_Set marker
K28.6
X
0
1
DC
K28.7
X
0
1
FC
Two will have caused byte realignment
K23.7
X
0
1
F7
/E/ K30.7
X
1
FE
Error
Any other
X
1
= XGMII ERROR reg.(Note 3)
Error Code, Default 1FF’h, see Table 3-19
NOTES:
1. First incoming IDLE only, subsequent IDLEs in that block repeat first received code.
2. If the XAUI_EN bit is set, the BBT3420 acts as though the TRANS_EN bit is set.
3. The XGMII IDLE character is set by the XGMII IDLE register, address 1B’h/C003’h (see Table 3-26), default value 07’h, combined with the K bit.
The XGMII ERROR code is similarly set by the XGMII ERROR register, address 16’h/C002’h (see Table 3-19)
BBT3420
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