9 TX_SDR 1 = SDR 0 = DDR 0’b R/W Single data rate on XGMII interface of transmitter. 8VDDQ
參數(shù)資料
型號： BBT3420-SN
廠商： Intersil
文件頁數(shù)： 11/38頁
文件大?。?/td> 0K
描述： TXRX QUAD MULTI-RATE 289-EBGA
標(biāo)準(zhǔn)包裝： 84
類型： 收發(fā)器
驅(qū)動器/接收器數(shù)： 4/4
規(guī)程： XAUI，XGMII，MDC/MDIO
電源電壓： 1.7 V ~ 1.9 V
安裝類型： 表面貼裝
封裝/外殼： 289-BGA
供應(yīng)商設(shè)備封裝： 289-BGA（19x19）
包裝： 托盤
19
9
TX_SDR
1 = SDR
0 = DDR
0’b
R/W
Single data rate on XGMII interface of transmitter.
8VDDQ_ASNS_EN 0=enable
1=disable
0’b
R/W
Automatically detect VDDQ power supply level and adjust
parallel output buffer driving strength.
7
HSTL_DRIVE
0=enable
1=disable
0’b
R/W
Increase parallel output buffer driving strength (if autosense
disabled).
6:4
LOS_CONTROL
0’h = 160mVP-P
1’h = 240mVP-P
2’h = 200mVP-P
3’h = 120mVP-P
4’h = 80mVP-P
else = 160mVP-P
000’b
R/W
Set the threshold voltage for the Loss Of Signal (LOS)
detection circuit. Nominal levels are listed for each control
value. Note 2
3
SC_RBC
1=source sync
0=source center
0’b
R/W
Timing of outgoing Receive Byte Clock (RBC) to Receive data
2
AKR_EN
1 = enable random
A/K/R
0 = /K/ only
0’b
R/W
Enable pseudo-random A/K/R (Note 1) in Inter Packet Gap
(IPG) on transmitter side (vs. /K/ only)
1
SOFT_RESET
Write 1 to initiate.
0’b
R/W SC
Reset the entire chip except MII register settings
0
Reserved
NOTES:
1. These state machines are implemented according to 802.3ae-2002 clause 48.
2. Please refer to section “3.7.2 Loss of Signal (LOS)” on page 6 for a more detailed description.
TABLE 3-28. MISCELLANEOUS CONTROL REGISTER 3 (CLAUSE 22) (Continued)
MII REgister 29, ADDRESS = 1D’h
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
TABLE 3-29. SPECIAL TEST FUNCTION CONTROL REGISTER
MII REGISTER 30 & 49159, ADDRESSES = 1E’h & C007’h
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
15:0
reserved
AAAA’h
R/W
Internal Function. DO NOT ALTER THIS REGISTER in BBT3420
TABLE 3-30. HALF RATE CLOCK CONTROL REGISTER
MII REGISTER 31 & 49160, ADDRESSES = 1F’h & C008’h
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
15:4
reserved
0’h
R/W
3
HALF_RATED
1’b = half rate clock
0’b
R/W
Channel D is running at half-rate clock speed
2
HALF_RATEC
1’b = half rate clock
0’b
R/W
Channel C is running at half-rate clock speed
1
HALF_RATEB
1’b = half rate clock
0’b
R/W
Channel B is running at half-rate clock speed
0
HALF_RATEA
1’b = half rate clock
0’b
R/W
Channel A is running at half-rate clock speed
BBT3420
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