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參數(shù)資料
| 型號： | BBT3420-SN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX QUAD MULTI-RATE 289-EBGA |
| 標準包裝： | 84 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | XAUI，XGMII，MDC/MDIO |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 289-BGA |
| 供應商設備封裝： | 289-BGA（19x19） |
| 包裝： | 托盤 |
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10
3.11 Serial Management Interface
The BBT3420 implements both the Management Interface
defined in IEEE 802.3 Clause 22, and that defined in Clause
45. This two-pin interface allows serial read/write of the
internal control registers and consists of the MDC clock and
MDIO data terminals. The PADR[4..0] pins are used to select
the address to which a given BBT3420 device responds.
The remainder of the MDIO frame and access details
depend on the respective formats. The BBT3420
automatically detects which format is being used on a frame-
by-frame basis, based on the second START bit. The two
formats are shown in Table 3-4, together with the references
to the respective IEEE 802.3 specifications. The fields are as
follows:
PRE, the Preamble field: at least 32 consecutive ‘1’ bits.
The BBT3420 will accept any number
≥32.
ST, the Start of Frame; for Clause 22, <01>; for Clause 45,
<00>.
OP, the Operation code; for Clause 22, Read and Write
operations are defined, all other values are invalid; for
Clause 45, additional operations to send the 16-bit
(indirect) register address, and to read data and (then)
increment the stored address are added.
PHYAD/PRTAD; the PHYsical (Clause 22) or PoRT
(Clause 45) hardware ADdress; this 5-bit address must
match the PADR pins on the BBT3420.
REGAD, REGister ADdress (Clause 22); this 5-bit address
specifies the register address. Replaced by the 16-bit
address value in Clause 45 format.
DEVAD, DEVice ADdress (Clause 45); this 5-bit address
specifies which MMD at any given port is being
possible values the BBT3420 will respond to.
TA, the TurnAround; allows time to avoid contention for a
read operation on the MDIO line.
DATA; the 16 bit data values to be written to or being read
from the BBT3420.
ADDRESS (Clause 45); this 16-bit address specifies the
register address for subsequent Clause 45 read or write
operations. A Read Increment operation will post-
increment the value.
IDLE; this condition flags the end of the frame. Since the
IEEE specification calls for a pullup on the MDIO line, this
effectively provides the MMD with a ‘1’ character, which
can be the beginning of the next PREamble.
3.12 Clause 22 PHY Addressing
The PADR[4..0] hardware address pins control the PHYAD
value, allowing use of up to 31 BBT3420 (or other
compatible) devices on any MDC/MDIO line pair. Each
device may contain up to 32 registers, some of which are
defined by the IEEE standard, the others being Vendor-
defined. The Clause 22-accessible registers are listed in
3.13 Clause 45 PHY Addressing
The PADR[4..0] hardware address pins control the PRTAD
(Port Address) value, each port normally consisting of a
series of MDIO Managed Devices (MMDs). Each of the up to
31 Ports may include up to 31 different devices, of which the
current specification defines 6 types, and allows vendor
specification of two others. The native-mode BBT3420
corresponds to two of the defined types; it can be either a
PHY XS (DEVAD = 4) or a DTE XS (DEVAD = 5), but may
also be used as part of another defined type, or as a
TABLE 3-4. MDIO MANAGEMENT FRAME FORMATS
Clause 22 Format (from Table 22-10 in IEEE Std 802.3-2002)
Opern
PRE
ST
OP
PHYAD
REGAD
TA
DATA
IDLE
Read
1....1
01
10
PPPPP
RRRRR
Z0
DDDDDDDDDDDDDDDD
Z
Write
1....1
01
PPPPP
RRRRR
10
DDDDDDDDDDDDDDDD
Z
Clause 45 Format (from Table 45-64 in IEEE 802.3.ae-2002)
Opern
PRE
ST
OP
PRTAD
DEVAD
TA
ADDRESS/DATA
IDLE
Addrs
1....1
00
PPPPP
DDDDD
10
AAAAAAAAAAAAAAAA
Z
Write
1....1
00
01
PPPPP
DDDDD
10
DDDDDDDDDDDDDDDD
Z
Read
1....1
00
11
PPPPP
DDDDD
Z0
DDDDDDDDDDDDDDDD
Z
Read Inc
1....1
00
10
PPPPP
DDDDD
Z0
DDDDDDDDDDDDDDDD
Z
TABLE 3-5. DEVAD DEVICE ADDRESS SETUP TABLE
MFD
MFC
DEVAD
VALUE
DEFAULT
IEEE
DEFINITION
1
DEVAD = 5
(000101’b)
11’b
DTE XS (XGXS
Device)
1
0
DEVAD = 4
(00100’b)
PHY XS (XGXS
Device)
0
1
DEVAD = 31
(11111’b)
Vendor Specific
0
DEVAD = 30
(11110’b)
Vendor Specific
BBT3420
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