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參數(shù)資料
| 型號： | BBT3420-SN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 18/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX QUAD MULTI-RATE 289-EBGA |
| 標準包裝： | 84 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | XAUI，XGMII，MDC/MDIO |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 289-BGA |
| 供應商設備封裝： | 289-BGA（19x19） |
| 包裝： | 托盤 |
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25
R10
TDD8
Input
Transmit Data/ K-code Flag, Channel D. When PSYNC is low, data on this pin is clocked
on the rising and falling edges of TCD. When PSYNC is high, data on this bus is clocked
on the rising and falling edges of TCA. When CODE is low, this pin is the 9th bit of an
8b/10b-encoded byte to be transmitted. When CODE is high, this pin acts as the K-
character generator indicator. When high, this pin causes the data on TDD(0-7) to be
encoded into a K-character.
T10
TDD9
Input
Transmit Data Pin, Channel D. When PSYNC is low, data on this pin is clocked on the
rising and falling edges of TCD. When PSYNC is high, data on this bus is clocked on the
rising and falling edges of TCA. When CODE is low, this pin is the 10th bit of an 8b/10b-
encoded byte. When CODE is high, this pin is undefined.
R11, T11, N12, P12,
R12, R13, T13, U13
RDD(0-7)
Output
Receive Data Pins, Channel D. When PSYNC is low, parallel data on this bus is valid on
the rising and falling edges of RCD. When PSYNC is high, data on this bus is valid on
the rising and falling edges of RCA.
T14
RDD8
Output
Receive Data/ K-code Flag, Channel D. When PSYNC is low, data on this pin is valid on
the rising and falling edges of RCD. When PSYNC is high, data on this pin is valid on
the rising and falling edges of RCA. When CODE is low, this pin is the 9th bit of a
received 8b/10b-encoded byte. When CODE is high, this pin acts as the K-character
flag. When high, this indicates the data on RDD(0-7) is a valid K-character.
U14
RDD9
Output
Receive Data Pin/ Error Detect, Channel D. When PSYNC is low, data on this pin is valid
on the rising and falling edges of RCD. When CODE is low, this pin is the 10th bit of an
8b/10b-encoded byte. When CODE is high, this pin goes high when to signify the
occurrence of either a parity error or an invalid code word during the decoding of the
received data.
TABLE 4-3. PARALLEL SIDE DATA PINS (Continued)
PIN#
NAME
TYPE
DESCRIPTION
TABLE 4-4. JTAG INTERFACE
PIN#
NAME
TYPE
DESCRIPTION
B3
TDI
Input
(w/pullup)
JTAG Input Data
A2
TDO
Output
JTAG Output Data
B2
TMS
Input
(w/pullup)
JTAG Mode Select
A3
TCLK
Input
(w/pulldown)
JTAG Clock
A1
TRSTN
Input
(w/pullup)
JTAG Reset
TABLE 4-5. MANAGEMENT DATA INTERFACE
PIN#
NAME
TYPE
DESCRIPTION
U3
MDIO
I/O
Management Address/Data I/O
U2
MDC
Input
Management Interface Clock
R1, T1, T3, T2, R2
PADR(0-4)
Input
Management Address (PHYAD for Clause 22, PRTAD for Clause 45). See also
MFD & MFC in next table for DEVAD control in Clause 45.
BBT3420
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