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參數(shù)資料
| 型號： | BBT3420-SN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 33/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX QUAD MULTI-RATE 289-EBGA |
| 標準包裝： | 84 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | XAUI，XGMII，MDC/MDIO |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 289-BGA |
| 供應(yīng)商設(shè)備封裝： | 289-BGA（19x19） |
| 包裝： | 托盤 |
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4
3.0 Detailed Functional Description
3.1 Transmit Parallel Input Modes
The parallel side of each of the channels in BBT3420 may
operate in either a 10-bit mode or a XGMII 9-bit mode. The
parallel input mode selection is controlled by the CODE pin
(Table 4-6) and the CODECENA bit in the MDIO register at
address 11’h in Clause 22 format (Table 3-16) and/or C000’h
in Clause 45 format (Table 3-32). In order to program the
device for XGMII 9-bit mode, the CODE pin should be set
HIGH and the CODECENA bit set to 1’b. For the 10-bit
Mode setting, either the CODE pin should be set to LOW or
the CODECENA bit should be set to 0’b.
3.1.1 10-BIT MODE
In the 10-bit mode the 8b/10b Codec is disabled, and the
externally encoded data are latched in the DDR input
registers in increments of 10 bits. In this case, the user is
responsible for generating and applying the proper input in
the form of ordered sets, data, and correct ‘comma’ group
signals, to ensure data coherence. The LSB (TDX[0]) is
shifted out first on the serial side, and the MSB (TDX[9]) is
shifted out last.
3.1.2 XGMII 9-BIT (8 BITS PLUS K CONTROL BIT) MODE
In the XGMII 9-bit mode, the unencoded data are latched in
the DDR input registers in 9 bits at a time. The lower 8 bits
(TD[A..D][7:0]) are byte-wide data or control values, and the
9th bit (TD[A..D][8]) is the "K" bit used to select special
control characters for link management. In this mode, the
10th bit (TD[A..D][9]) is used for disparity error or code
violation. The 8b/10b Codec is enabled, and converts the
data and the valid control values.
The XGMII IDLE Code Register (Clause 22 Address 1B’h or
Clause 45 Address C003’h) controls the data pattern that
represents an IDLE character. The default value of this
register is 07’h. The register can be programmed to any 8-bit
value excluding the already defined (control) values shown
in Table 3-1.
When both the TRANS_EN bit (Clause 22 Address 10’h in
Table 3-15 or Clause 45 Address C001’h in Table 3-33) and
the AKR_EN bit (Clause 22 Address 1D’h in Table 3-28 or
Clause 45 Address C001’h in Table 3-33) are set to 1, or
when the XAUI_EN bit is set, the IDLE character data
pattern will be sequenced into /A/, /K/, and /R/ codes (IEEE
802.3ae-2002 specified). Alternatively, if neither of the
AKR_EN or XAUI_EN bits are set, the XGMII IDLE and the
/K/ code will both be transmitted as the XAUI /K/ code, and
the /A/ and /R/ control codes will be transmitted as XAUI /A/
and /R/ codes respectively. The 8b/10b encoding patterns
are described in Table 3-1. For valid operation, the XGMII
and XAUI Lane 0 signals should be connected to the
BBT3420 Channel A pins.
When the XAUI_EN bit is set to 1, if a local/remote fault is
received on the XAUI inputs, it will be passed as ||LF|| or
||RF|| Sequence Ordered_sets respectively, i.e.,
/K28.4/D0.0/D0.0/D1.0(D2.0)/. Local fault is declared when
any of the following conditions are detected:
1. No signal is detected in any one of four channels.
2. No valid comma is detected in any one or more of the four
channels.
3. When all the channels are not deskewed.
When the XAUI_EN bit is set to 1, if a local/remote fault
K28.4/D0.0/D0.0/D1.0(D2.0)/ is written to the XGMII transmit
interface for XAUI transmission, the ||LF|| or ||RF|| Sequence
Ordered_set is transmitted according to the IEEE 802.3ae-
2002 randomizing algorithm. Any other Sequence
Ordered_set will also be transmitted in the same way.
TABLE 3-1. VALID 8B/10B ENCODER PATTERNS
TRANSMITTING SERDES
NOTES and
DESCRIPTION
K-BIT
TD DATA
TRANS_EN
BIT (Note 1)
AKR_EN BIT
(Note 1)
SERIAL
CHARACTER
SERIAL
CODE
0
0-FF’h
X
See 802.3-2002 Table36-1
Valid Data Value
1
= XGMII IDLE reg.
(Note 2) (default 07’h)
0
X
Invalid code
1
0
/K/
K28.5
Comma (Sync)
1
/A/ /K/ /R/
IEEE802.3ae 48.2.4.2 algorithm
1
BC
X
0
/K/
K28.5
Comma (Sync)
1
/A/ /K/ /R/
IEEE802.3ae 48.2.4.2 algorithm
1
7C
X
0
/A/
K28.3
Align
1
/A/ /K/ /R/
IEEE802.3ae 48.2.4.2 algorithm
1
1C
X
0
/R/
K28.0
Alternate Idle (Skip)
1
/A/ /K/ /R/
IEEE802.3ae 48.2.4.2 algorithm
1FB
X
/S/
K27.7
Start
BBT3420
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