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參數(shù)資料
| 型號： | BBT3420-SN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX QUAD MULTI-RATE 289-EBGA |
| 標準包裝： | 84 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | XAUI，XGMII，MDC/MDIO |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 289-BGA |
| 供應商設(shè)備封裝： | 289-BGA（19x19） |
| 包裝： | 托盤 |
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20
TABLE 3-31. LOS STATUS REGISTER (CLAUSE 45)
MII REGISTER 49161, ADDRESS = C009’h
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
15:8
Reserved
7:4
Internal
F’h
RO
Internal Function (ignore)
3
LOS_D
1 = Signal less than
threshold
0 = Signal greater
than threshold
0’b
RO/LH
(Note 1)
Loss Of Signal for RX Inputs of each of 4 channels; signal less
than LOS_CONTROL value (see Table 3-28 and/or Table 3-33)
(Note 2)
2
LOS_C
0’b
1
LOS_B
0’b
0
LOS_A
0’b
NOTES:
1. These bits are latched high on any LOS condition detected. They are reset low on being read.
2. Please refer to section“3.7.2 Loss of Signal (LOS)” on page 6 for a more detailed description.
TABLE 3-32. MISCELLANEOUS CONTROL REGISTER 1 (CLAUSE 45)
MII REGISTER 49152, ADDRESS = C000’h
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
15:14
Reserved
00’b
Always write to 00’b
13
VDDQ_ASNS_EN
0=enable
1=disable
0’b
R/W
Automatically detect VDDQ power supply level and
adjust parallel output buffer driving strength.
12
HSTL_DRIVE
0=enable
1=disable
0’b
R/W
Increase parallel output buffer driving strength (if
autosense disabled).
11
SC_RBC
1=source sync
0=source center
0’b
R/W
Timing of outgoing Receive Byte Clock (RBC) to
Receive data
10
CODECENA
1=enable if CODE pin hi
0=disable
1’b
R/W
Internal 8b/10b Codec enable/disable
9:8
CDET[1:0]
Bit 7 controls positive comma
detection, Bit 6 controls negative
comma detection
0’b=disable
1’b=enable
11’b
R/W
Comma Detect Select. These bits enable detection
of positive, negative, or both positive and negative
disparities of comma, or disable detection of either.
7
DSKW_SM_EN
0=disable
1=enable
0’b
R/W
Enable De-skew state machine control (Note 1) .
Overridden enabled by XAUI_EN; see Table 3-28
and/or Table 3-33. May not operate correctly unless
the PCS_SYNC_EN bit is also set.
6:5
RCLKMODE
See Table 3-22 for a description of
these bits, and their interaction with
the PSYNC and RETIMER pins.
Received Clock Mode. These two bits, together with
the PSYNC and RETIMER pins, select which clock
the received data is aligned to.
4
PCS_SYNC_EN
0=disable
1=enable
0’b
R/W
Enable 8b/10b PCS coding synchronized state
machine (Note 1) to control the byte alignment (IEEE
code-group alignment’) of the high speed
deserializer. Overridden enabled by XAUI_EN; see
Table 3-28 and/or Table 3-33.
3
IDLE_D_EN
1=enabled
0=disabled
1’b
R/W
Enables IDLE vs. NON-IDLE detection for channel
alignment.
2
ELST_EN
1=enabled
0=disabled
1’b
R/W
Enable the elastic function of the receiver buffer
1
A_ALIGN _DIS
1=disabled
0=enabled
1’b
R/W
Receiver aligns data on incoming "\/A/" characters
(K28.3). If disabled (default), receiver aligns data on
IDLE to non-IDLE transitions (if bit 3 set). Overridden
enabled by XAUI_EN; see Table 3-28 and/or Table 3-
BBT3420
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