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參數(shù)資料
| 型號： | AV80C52TXXX-20:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 1.40 MM HEIGHT, VQFP-44 |
| 文件頁數(shù)： | 3/134頁 |
| 文件大?。?/td> | 3805K |
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100
8068U–AVR–06/2013
XMEGA A3
Not recommended for new designs -
Use XMEGA A3U series
36.1.2
rev. B
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
ADC has increased INL error for some operating conditions
ADC gain stage output range is limited to 2.4 V
ADC Event on compare match non-functional
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
Configuration of PGM and CWCM not as described in XMEGA A Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
DAC has increased INL or noise for some operating conditions
DAC refresh may be blocked in S/H mode
Conversion lost on DAC channel B in event triggered mode
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
NMI Flag for Crystal Oscillator Failure automatically cleared
Writing EEPROM or Flash while reading any of them will not work
Crystal start-up time required after power-save even if crystal is source for RTC
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag (DIF) erroneously read as set
WDR instruction inside closed window will not issue reset
1.
Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for another AC, the first comparator will be affected for up to
1 s and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
2.
VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
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