參數(shù)資料
型號： AV80C52TXXX-20:D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44
封裝： 1.40 MM HEIGHT, VQFP-44
文件頁數(shù)： 12/134頁
文件大?。?/td> 3805K
109
8011Q–AVR–02/2013
ATmega164P/324P/644P
12.9.5
OCR0B – Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
12.9.6
TIMSK0 – Timer/Counter Interrupt Mask Register
Bits 7:3 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, that is, when the OCF0B bit is set in the
Timer/Counter Interrupt Flag Register – TIFR0.
Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, that is, when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR0.
12.9.7
TIFR0 – Timer/Counter 0 Interrupt Flag Register
Bits 7:3 – Res: Reserved Bits
These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero.
Bit
76543210
OCR0B[7:0]
OCR0B
Read/Write
R/W
Initial Value
00000000
Bit
7
6
5
4
3
2
1
0
–
OCIE0B
OCIE0A
TOIE0
TIMSK0
Read/Write
RRRR
R
R/W
Initial Value
0
Bit
7
6
543210
––
–––
OCF0B
OCF0A
TOV0
TIFR0
Read/Write
RRRRR
R/W
Initial Value
0
000000
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