參數(shù)資料
型號： AV80C51T-12R
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44
文件頁數(shù)： 136/170頁
文件大?。?/td> 4133K
代理商： AV80C51T-12R
68
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Figure 11-11. Phase and Frequency Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set at the same timer clock cycle as the OCR0x Registers are updated
with the double buffer value (at BOTTOM). When either OCR0A or ICR0 is used for defining the TOP value, the
OC0A or ICF0 flag set when TCNT0 has reached TOP. The interrupt flags can then be used to generate an inter-
rupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNT0 and the OCR0x.
As Figure 11-11 on page 68 shows the output generated is, in contrast to the phase correct mode, symmetrical in
all periods. Since the OCR0x Registers are updated at BOTTOM, the length of the rising and the falling slopes will
always be equal. This gives symmetrical output pulses and is therefore frequency correct.
Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using ICR0, the OCR0A
Register is free to be used for generating a PWM output on OC0A. However, if the base PWM frequency is actively
changed by changing the TOP value, using the OCR0A as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC0x
pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be gen-
erated by setting the COM0x1:0 to three (See Table 11-4 on page 73). The actual OC0x value will only be visible
on the port pin if the data direction for the port pin is set as output (DDR_OC0x). The PWM waveform is generated
by setting (or clearing) the OC0x Register at the compare match between OCR0x and TCNT0 when the counter
increments, and clearing (or setting) the OC0x Register at compare match between OCR0x and TCNT0 when the
counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be cal-
culated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1
2
3
4
TCNTn
Period
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
f
OCnxPFCPWM
f
clk_I/O
2NTOP
-----------------------------
=
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