參數(shù)資料
型號： AV80C51T-12R
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44
文件頁數(shù)： 128/170頁
文件大?。?/td> 4133K
代理商： AV80C51T-12R
60
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
11.6.2
Compare Match Blocking by TCNT0 Write
All CPU writes to the TCNT0 Register will block any compare match that occurs in the next timer clock cycle, even
when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without trigger-
ing an interrupt when the Timer/Counter clock is enabled.
11.6.3
Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNT0 when using any of the Output Compare channels, independent of whether
the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the compare match will
be missed, resulting in incorrect waveform generation. Do not write the TCNT0 equal to TOP in PWM modes with
variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting.
The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output.
The easiest way of setting the OC0x value is to use the Force Output Compare (0x) strobe bits in Normal mode.
The OC0x Register keeps its value even when changing between Waveform Generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the
COM0x1:0 bits will take effect immediately.
11.7
Compare Match Output Unit
The Compare Output Mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0
bits for defining the Output Compare (OC0x) state at the next compare match. Secondly the COM0x1:0 bits control
the OC0x pin output source. Figure 11-7 on page 61 shows a simplified schematic of the logic affected by the
COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the
general I/O port control registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When refer-
ring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur,
the OC0x Register is reset to “0”.
相關(guān)PDF資料
PDF描述
AF180C51T-16D 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
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