參數(shù)資料
型號(hào)： AV80C51T-12R
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44
文件頁數(shù)： 11/170頁
文件大?。?/td> 4133K
代理商： AV80C51T-12R
108
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Notes:
1. This section is read-only.
Notes:
1. This section is read-only.
15.3.3
Configuration Section
ATtiny4/5/9/10 have one configuration byte, which resides in the configuration section. See Table 15-5.
Table 15-6 briefly describes the functionality of all configuration bits and how they are mapped into the configura-
tion byte.
Configuration bits are not affected by a chip erase but they can be cleared using the configuration section erase
command (see “Erasing the Configuration Section” on page 112). Note that configuration bits are locked if Non-
Volatile Lock Bit 1 (NVLB1) is programmed.
15.3.3.1
Latching of Configuration Bits
All configuration bits are latched either when the device is reset or when the device exits the external programming
mode. Changes to configuration bit values have no effect until the device leaves the external programming mode.
Table 15-4.
Number of Words and Pages in the Flash (ATtiny4/5)
Section
Size (Bytes)
Page Size (Words)
Pages
WADDR
PADDR
Code (program memory)
512
8
32
[3:1]
[9:4]
Configuration
8
1
[3:1]
–
Signature (1)
16
8
2
[3:1]
[4:4]
Calibration (1)
8
1
[3:1]
–
Table 15-5.
Configuration bytes
Configuration word address
Configuration word data
High byte
Low byte
0x00
Reserved
Configuration Byte 0
0x01 ... 0x07
Reserved
Table 15-6.
Configuration Byte 0
Bit
Bit Name
Description
Default Value
7:3
–
Reserved
1 (unprogrammed)
2
CKOUT
System Clock Output
1 (unprogrammed)
1
WDTON
Watchdog Timer always on
1 (unprogrammed)
0
RSTDISBL
External Reset disable
1 (unprogrammed)
相關(guān)PDF資料
PDF描述
AF180C51T-16D 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
AF180C51-30D 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP44
AT80C51-25R 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP44
AS80C31-36D 8-BIT, 36 MHz, MICROCONTROLLER, PQCC44
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