參數資料
型號: ATTINY43U-SUR
廠商: Atmel
文件頁數: 37/158頁
文件大小: 0K
描述: MCU AVR 4KB FLASH 8MHZ 20SOIC
產品培訓模塊: tinyAVR Introduction
標準包裝: 1,000
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: USI
外圍設備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數: 16
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數據轉換器: A/D 4x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
其它名稱: ATTINY43U-SUR-ND
131
8048C–AVR–02/12
ATtiny43U
16.13.3.2
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADCSRB, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
ADC[9:0]: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on
16.13.4
ADCSRB – ADC Control and Status Register B
Bit 5 – Res: Reserved Bit
This bit is reserved and will always read what was written.
Bit 4 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a comple the description of this bit, see “ADCL and ADCH – ADC Data Register” on
Bit 3 – Res: Reserved Bit
This bit is reserved and will always read what was written.
Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a
trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
Bit
151413121110
9
8
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
ADC1
ADC0
ADCL
765
43
21
0
Read/Write
R
RR
R
Initial Value
0
000
00
0
Bit
7
6543
210
BS
ACME
ADLAR
ADTS2
ADTS1
ADTS0
ADCSRB
Read/Write
R
R/W
R
R/W
R
R/W
Initial Value
0
0000
000
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