參數(shù)資料
型號: ATTINY43U-SUR
廠商: Atmel
文件頁數(shù): 149/158頁
文件大?。?/td> 0K
描述: MCU AVR 4KB FLASH 8MHZ 20SOIC
產(chǎn)品培訓(xùn)模塊: tinyAVR Introduction
標(biāo)準包裝: 1,000
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: USI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
其它名稱: ATTINY43U-SUR-ND
90
8048C–AVR–02/12
ATtiny43U
OCRnA changes its value from MAX, like in Figure 12-7 on page 89. When the OCRnA value
is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of
an up-counting Compare Match.
The timer starts counting from a value higher than the one in OCRnA, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
12.8
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
Tn) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set. Figure 12-8 on page 90 contains timing data for basic Timer/Counter operation.
The figure shows the count sequence close to the MAX value in all modes other than phase cor-
rect PWM mode.
Figure 12-8. Timer/Counter Timing Diagram, no Prescaling
Figure 12-9 on page 90 shows the same timing data, but with the prescaler enabled.
Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O/8)
Figure 12-10 on page 91 shows the setting of OCFnB in all modes and OCFnA in all modes
except CTC mode and PWM mode, where OCRnA is TOP.
clk
Tn
(clk
I/O/1)
TOVn
clk
I/O
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)
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