參數(shù)資料
型號: ATTINY43U-SUR
廠商: Atmel
文件頁數(shù): 34/158頁
文件大?。?/td> 0K
描述: MCU AVR 4KB FLASH 8MHZ 20SOIC
產(chǎn)品培訓(xùn)模塊: tinyAVR Introduction
標準包裝: 1,000
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: USI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 64 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
其它名稱: ATTINY43U-SUR-ND
129
8048C–AVR–02/12
ATtiny43U
Bits 2:0 – MUX[2:0]: Analog Channel Selection Bits
The value of these bits selects which analog input is connected to the ADC, as shown in Table
16-4. Selecting channel ADC4 enables temperature measurement.
Notes:
1. After switching to internal voltage reference the ADC requires a settling time of 1ms before
measurements are stable. Conversions starting before this may not be reliable. The ADC must
be enabled during the settling time.
2. Due to the voltage divider present, a current will flow from VBAT to ground via a 100kΩ resistor
divider as long as this channel is selected.
If these bits are changed during a conversion, the change will not go into effect until this
conversion is complete (ADIF in ADCSRA is set).
16.13.2
ADCSRA – ADC Control and Status Register A
Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,
write this bit to one to start the first conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-
tion of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.
Bit 5 – ADATE: ADC Auto Trigger Enable
Table 16-4.
ADC Multiplexer Channel Selections.
Single Ended Input
MUX[2:0]
ADC0 (PA0)
000
ADC1 (PA1)
001
ADC2 (PA2)
010
ADC3 (PA3)
011
0V (GND)
100
Internal 1.1V Reference (1)
101
V
BAT
110
ADC4 (3)
111
Bit
7654
321
0
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
ADCSRA
Read/Write
R/W
Initial Value
0000
000
0
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