參數(shù)資料
型號(hào)： ATAM893T-TKSYD
廠商： Atmel
文件頁數(shù)： 8/98頁
文件大小： 0K
描述： IC MCU FLASH 4K MTP 20SSOP
標(biāo)準(zhǔn)包裝： 830
系列： MARC4
核心處理器： MARC4
芯體尺寸： 4-位
速度： 4MHz
連通性： SSI（2 線，3 線）
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲(chǔ)器容量： 4KB（4K x 8）
程序存儲(chǔ)器類型： EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量： 256 x 4
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 6.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 20-SOIC（0.209"，5.30mm 寬）
包裝： 管件
16
4680C–4BMCU–01/05
ATAM893-D
The clock module is programmable via software with the clock management register (CM) and
the system configuration register (SC). The required oscillator configuration can be selected with
the OS1 bit and the OS0 bit in the SC register. A programmable 4-bit divider stage allows the
adjustment of the system clock speed. A special feature of the clock management is that an
external oscillator may be used and switched on and off via a port pin for the power-down mode.
Before the external clock is switched off, the internal RC-oscillator 1 must be selected with the
CCS bit and then the SLEEP mode may be activated. In this state an interrupt can wake up the
controller with the RC-oscillator, and the external oscillator can be activated and selected by
software. A synchronization stage avoids clock periods that are too short if the clock source or
the clock speed is changed. If an external input clock is selected, a supervisor circuit monitors
the external input and generates a hardware reset if the external clock source fails or drops
below 500 kHz for more than 1 ms.
Figure 4-12. Clock Module
The clock module generates two output clocks. One is the system clock (SYSCL) and the other
the periphery (SUBCL). The SYSCL can supply the core and the peripherals and the SUBCL
can supply only the peripherals with clocks. The modes for clock sources are programmable
with the OS1 bit and OS0 bit in the SC register and the CCS bit in the CM register.
Ext. clock
ExIn
ExOut
Stop
RC oscillator 2
RCOut2
Stop
R
Trim
4-MHz oscillator
4Out
Stop
Oscin
Oscout
Oscin
Oscout
32-kHz oscillator
32Out
Oscin
Oscout
RC-
oscillator 1
RCOut1
Control
Stop
IN1
IN2
Cin
/2
Divider
Sleep
WDL
Osc-Stop
NSTOP
CCS
CSS1
CSS0
CM
BOT
- - -
OS1
OS0
SUBCL
SYSCL
SC
*
OSC1
*
OSC2
*
configurable
Cin/16
32 kHz
Table 4-4.
Clock Modes
Mode
OS1
OS0
Clock Source for SYSCL
Clock Source for
SUBCL
CCS = 1
CCS = 0
1
RC-oscillator 1 (intern)
External input clock
C
in/16
2
0
1
RC-oscillator 1 (intern)
RC-oscillator 2 with external
trimming resistor
C
in/16
3
1
0
RC-oscillator 1 (intern)
4-MHz oscillator
C
in/16
4
0
RC-oscillator 1 (intern)
32-kHz oscillator
32 kHz
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