參數(shù)資料
型號: ATF1502BE-5AX44
廠商: Atmel
文件頁數(shù): 1/24頁
文件大?。?/td> 0K
描述: IC CPLD 64MC 1.8V 44-TQFP
標準包裝: 160
系列: ATF15xx
可編程類型: 系統(tǒng)內(nèi)可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時間 tpd(1): 7.0ns
電壓電源 - 內(nèi)部: 1.7 V ~ 1.9 V
宏單元數(shù): 32
輸入/輸出數(shù): 32
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤
配用: ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S
Features
High-performance Fully CMOS, Electrically-erasable Complex Programmable
Logic Device
– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44 Pins
– 5.0 ns Pin-to-pin Propagation Delay
– Registered Operation up to 333 MHz
– Enhanced Routing Resources
– Optimized for 1.8V Operation
– 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.8V, 2.5V, 3.3V
In-System Programming (ISP) Supported
– 1.8V ISP Using IEEE 1532 (JTAG) Interface
– Boundary-scan Testing to IEEE JTAG Std. 1149.1 Supported
Flexible Logic Macrocell
– D/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate with Low Output Drive
– Programmable Open Collector Output Option
– Maximum Logic Utilization by Burying a Register with a COM Output and Vice
Versa
Fully Green (RoHS Compliant)
10 A Static Current
Power Saving Option During Operation Using PD1, PD2 Pins
Programmable Pin-keeper Option on Inputs and I/Os
Programmable Schmitt Trigger Option on Input and I/O Pins
Programmable Input and I/O Pull-up Option (per Pin)
Unused Pins Can Be Configured as Ground (Optional)
Available in Commercial and Industrial Temperature Ranges
Available in 44-lead TQFP
Advanced Digital CMOS Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 10-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
Security Fuse Feature
Hot-Socketing Supported
High-
performance
CPLD
ATF1502BE
Rev. 3492A–PLD–12/05
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