參數資料
| 型號： | ATF1502BE-5AX44 |
| 廠商： | Atmel |
| 文件頁數： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 64MC 1.8V 44-TQFP |
| 標準包裝： | 160 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 7.0ns |
| 電壓電源 - 內部： | 1.7 V ~ 1.9 V |
| 宏單元數： | 32 |
| 輸入/輸出數： | 32 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應商設備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
| 配用： | ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S |
10
3492A–PLD–12/05
ATF1502BE
All ATF1502BE devices are initially shipped in the erased state, thereby making them ready to
use for ISP.
Note:
For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”
application note.
6.
JTAG-BST/ISP Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1502BE. The boundary-scan technique involves the inclusion of a shift-register stage (con-
tained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing methods. Each input pin and I/O
pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The TAP controller
is automat ically reset at power -up. The five JTAG modes supported include:
SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1502BE’s ISP can be
fully described using JTAG’s BSDL as described in IEEE Standard 1149.1. This allows
ATF1502BE programming to be described and implemented using any one of the third-party
development tools supporting this standard.
The ATF1502BE has the option of using four JTAG-standard I/O pins for boundary-scan testing
(BST) and ISP purposes. The ATF1502BE is programmable through the four JTAG pins using
the IEEE standard JTAG programming protocol established by IEEE Standard 1532 using 1.8V
LVCMOS level programming signals from the ISP interface for in-system programming. The
JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG
control pins are available as I/O pins.
6.1
JTAG Boundary-scan Cell (BSC) Testing
The ATF1502BE contains 32 I/O pins and four input pins. Each input pin and I/O pin has its own
boundary-scan cell (BSC) in order to support boundary-scan testing as described in detail by
IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan registers and
up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the
macrocells. The BSCs in the device are chained together through the capture registers. Input to
the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin.
Capture registers are used to capture active device data signals, to shift data in and out of the
device and to load data into the update registers. Control signals are generated internally by the
JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells is shown
below.
相關PDF資料 |
PDF描述 |
|---|---|
| ATF1504ASVL-20QI100 | IC CPLD 20NS LOWV LOWPWR 100QPFP |
| ATF1504BE-5AX100 | IC CPLD 64MC 1.8V 100-TQFP |
| ATF1508ASL-25QI160 | IC CPLD 25NS LOW PWR 160PQFP |
| ATF1508ASVL-20JU84 | IC CPLD 20NS LOWV LOW PWR 84PLCC |
| ATF1508BE-5AX100 | IC CPLD 128MC 1.8V ISP 100TQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ATF1502BE-7AU44 | 功能描述:CPLD - 復雜可編程邏輯器件 32 MC CPLD 1.8V ISP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1502SE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Family Datasheet |
| ATF1502SE(L) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATF1502/04/08/16SE(L) Preliminary [Updated 9/02. 69 Pages] Second Generation Industry Compatible 5V Logic Doubling CPLDs 32-512 Macrocells. standard & low power w/ISP |
| ATF1502SE-10 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Family Datasheet |
| ATF1502SE-5 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Family Datasheet |
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