參數(shù)資料
型號: ATAM893T-TKSYD
廠商: Atmel
文件頁數(shù): 39/98頁
文件大?。?/td> 0K
描述: IC MCU FLASH 4K MTP 20SSOP
標(biāo)準(zhǔn)包裝: 830
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 管件
44
4680C–4BMCU–01/05
ATAM893-D
5.3.2.7
Duty Cycle Generator
The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at the duty
cycle generator output depends on the duty cycle and the Timer 2 prescaler setting. The DCG-
stage can also be used as an additional programmable prescaler for Timer 2.
Figure 5-23. DCG Output Signals
5.3.2.8
Timer 2 Mode Register 2 (T2M2)
Table 5-10.
Timer 2 Mode Select Bits
Mode
T2MS1
T2MS0
Clock Output (POUT)
Timer 2 Modes
1
4-bit counter overflow (OVF1)
12-bit compare counter, the DCG
have to be bypassed in this mode
2
1
0
4-bit compare output (CM1)
8-bit compare counter with 4-bit
programmable prescaler and duty
cycle generator
3
0
1
4-bit compare output (CM1)
8-bit compare counter clocked by
SYSCL or the external clock input
T2I, 4-bit prescaler run, the
counter 2/1 starts after writing
mode 3
4
0
4-bit compare output (CM1)
8-bit compare counter clocked by
SYSCL or the external clock input
T2I, 4-bit prescaler stop and
resets
DCGIN
DCGO0
DCGO1
DCGO2
DCGO3
Address: '7'hex — Subaddress: '2'hex
Bit 3Bit 2Bit 1Bit 0
T2M2
T2TOP
T2OS2
T2OS1
T2OS0
Reset value: 1111b
T2TOP
Timer 2 Toggle Output Preset
This bit allows the programmer to preset the Timer 2 output T2O.
T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0)
T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1)
Note: If T2R = 1, no output preset is possible
T2OS2
Timer 2 Output Select bit 2
T2OS1
Timer 2 Output Select bit 1
T2OS0
Timer 2 Output Select bit 0
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