參數(shù)資料
型號: ATAM893T-TKSYD
廠商: Atmel
文件頁數(shù): 30/98頁
文件大?。?/td> 0K
描述: IC MCU FLASH 4K MTP 20SSOP
標(biāo)準(zhǔn)包裝: 830
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 管件
36
4680C–4BMCU–01/05
ATAM893-D
5.3.2
Timer 2
Timer 2 is an 8/12-bit timer used for:
Interrupt, square-wave, pulse and duty cycle generation
Baud-rate generation for the internal shift register
Manchester and Bi-phase modulation together with the SSI
Carrier frequency generation and modulation together with the SSI
Timer 2 can be used as interval timer for interrupt generation, as signal generator or as baud-
rate generator and modulator for the serial interface. It consists of a 4-bit and an 8-bit up counter
stage which both have compare registers. The 4-bit counter stages of Timer 2 are cascadable
as a 12-bit timer or as an 8-bit timer with a 4-bit prescaler. The timer can also be configured as
an 8-bit timer and separate a 4-bit prescaler.
The Timer 2 input can be supplied via the system clock, the external input clock (T2I), the Timer
1 output clock, the Timer 3 output clock or the shift clock of the serial interface. The external
input clock T2I is not synchronized with SYSCL. Therefore, it is possible to use Timer 2 with a
higher clock speed than SYSCL. Furthermore, with that input clock the Timer 2 operates in the
power-down mode SLEEP (CPU core
sleep and OSC-Stop yes) as well as in POWER-
DOWN (CPU core
sleep and OSC-Stop no). All other clock sources supply no clock signal in
SLEEP if NSTOP = 0. The 4-bit counter stages of Timer 2 have an additional clock output
(POUT).
Its output has a modulator stage that allows the generation of pulses as well as the generation
and modulation of carrier frequencies. The Timer 2 output can modulate with the shift register
data output to generate Bi-phase- or Manchester code.
If the serial interface is used to modulate a bit-stream, the 4-bit stage of Timer 2 has a special
task. The shift register can only handle bit-stream lengths divisible by 8. For other lengths, the
4-bit counter stage can be used to stop the modulator after the right bit-count is shifted out.
If the timer is used for carrier frequency modulation, the 4-bit stage works together with an addi-
tional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier frequency and duty
cycle. The 8-bit counter is used to enable and disable the modulator output for a programmable
count of pulses.
For programming the time interval, the timer has a 4-bit and an 8-bit compare register. For pro-
gramming the timer function, it has four mode and control registers. The comparator output of
stage 2 is controlled by a special compare mode register (T2CM). This register contains mask
bits for the actions (counter reset, output toggle, timer interrupt) which can be triggered by a
compare match event or the counter overflow. This architecture enables the timer function for
various modes.
Table 5-7.
Watchdog Time Control Bits
WDT1
WDT0
Divider
Delay Time to Reset with
SUBCL = 32 kHz
Delay Time to Reset with
SYSCL = 2/1 MHz
0
512
15.625 ms
0.256 ms/0.512 ms
0
1
2048
62.5 ms
1.024 ms/2.048 ms
1
0
16384
0.5 s
8.2 ms/16.4 ms
1
131072
4 s
65.5 ms/131 ms
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