參數(shù)資料
型號(hào): ATAM893T-TKSYD
廠商: Atmel
文件頁(yè)數(shù): 22/98頁(yè)
文件大?。?/td> 0K
描述: IC MCU FLASH 4K MTP 20SSOP
標(biāo)準(zhǔn)包裝: 830
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 管件
29
4680C–4BMCU–01/05
ATAM893-D
5.2.4
Bi-directional Port 4
The bi-directional Port 4 is a bit-wise configurable I/O port and provides the external pins for the
Timer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in exactly the
same way as bi-directional Port 2 (see Figure 5-6). Two additional multiplexes allow data and
port direction control to be passed over to other internal modules (Timer 2, VM or SSI). The I/O
pins for the SC and SD lines have an additional mode to generate an SSI-interrupt.
All four Port 4 pins can be individually switched by the P4CR register. Figure 5-6 shows the inter-
nal interfaces to bi-directional Port 4.
Figure 5-6.
Bi-directional Port 4 and Port 6
Table 5-3.
Port 5 Control Register
Auxiliary Address: '5'hex First Write Cycle
Second Write Cycle
Code
3 2 1 0
Function
Code
3 2 1 0
Function
x x 1 1
BP50 in input mode – interrupt disabled
x x 1 1
BP52 in input mode – interrupt disabled
x x 0 1
BP50 in input mode – rising edge interrupt
x x 0 1
BP52 in input mode – rising edge interrupt
x x 1 0
BP50 in input mode – falling edge interrupt
x x 1 0
BP52 in input mode – falling edge interrupt
x x 0 0
BP50 in output mode – interrupt disabled
x x 0 0
BP52 in output mode – interrupt disabled
1 1 x x
BP51 in input mode – interrupt disabled
1 1 x x
BP53 in input mode – interrupt disabled
0 1 x x
BP51 in input mode – rising edge interrupt
0 1 x x
BP53 in input mode – rising edge interrupt
1 0 x x
BP51 in input mode – falling edge interrupt
1 0 x x
BP53 in input mode – falling edge interrupt
0 0 x x
BP51 in output mode – interrupt disabled
0 0 x x
BP53 in output mode – interrupt disabled
Master reset
Q
V
DD
BPxy
(1) Flash options
PxDATy
I/O Bus
D
I/O Bus
Switched
pull-up
Switched
pull-down
S
PxCRy
S
Q
D
PxMRy
POut
(Direction)
PDir
Intx
(1)
PIn
Static
pull-up
Static
pull-down
V
DD
V
DD
(1)
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