- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄381451 > AT43USB355M-AU (ATMEL CORP) Full-speed USB Microcontroller with Embedded Hub, ADC and PWM PDF資料下載
參數(shù)資料
| 型號(hào)： | AT43USB355M-AU |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Full-speed USB Microcontroller with Embedded Hub, ADC and PWM |
| 中文描述： | 8-BIT, MROM, 12 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 1.40 MM, GREEN, PLASTIC, MS-026ACB, LQFP-64 |
| 文件頁(yè)數(shù)： | 87/115頁(yè) |
| 文件大小： | 610K |
| 代理商： | AT43USB355M-AU |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)當(dāng)前第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)
87
AT43USB355
2603G–USB–04/06
Hub End-point 0 Control and Acknowledge Register – HCAR0
Function End-point 0 Control and Acknowledge Register – FCAR0
Bit 7
–
DIR: Control transfer direction
It is set by the microcontroller firmware to indicate the direction of a control transfer to the USB
hardware. The FW writes to this bit location after it receives an RX SETUP interrupt. The hard-
ware uses this bit to determine the status phase of a control transfer.
0 = control write or no data stage
1 = control read
Bit 6
–
DATA END
When set to 1 by firmware, this bit indicate that the microcontroller has either placed the last
data packet in FIFO, or that the microcontroller has processed the last data packet it expects
from the Host. This bit is used by control end-points only together with bit 4 (TX Packet Ready)
to signal the USB hardware to go to the STATUS phase after the packet currently residing in
the FIFO is transmitted. After the hardware completes the STATUS phase it will interrupt the
microcontroller without clearing this bit.
Bit 5
–
FORCE STALL
This bit is set by the microcontroller to indicate a stalled end-point. The hardware will send a
STALL handshake as a response to the next IN or OUT token, or whenever there is a control
transfer without a Data Stage.
The microcontroller sets this bit if it wants to force a STALL. A STALL is sent if any of the fol-
lowing condition is encountered:
1.
An unsupported request is received.
2.
The host continues to ask for data after the data is exhausted.
3.
The control transfer has no data stage.
Bit 4
–
TX PACKET READY: Transmit Packet Ready
When set by the firmware, this bit indicates that the microcontroller has loaded the FIFO with a
packet of data. This bit is cleared by the hardware after the USB Host acknowledges the
packet. For ISO end-points, this bit is cleared unconditionally after the data is sent.
This bit is used for the following operations:
1.
Control read transactions by a control end-point.
2.
IN transactions with DATA1 PID to complete the status phase for a control end-point,
when this bit is zero but Data End set high (bit 4).
3.
By a BULK IN or ISO IN or INT IN end-point.
The microcontroller should write into the FIFO only if this bit is cleared. After it has completed
writing the data, it should set this bit. This data can be of zero length.
Bit
7
6
5
4
3
2
1
0
Hub EP0
$1FA7
DIR
DATA
END
FORCE
STALL
TX
PACKET
READY
STALL_
SENT_
ACK
RX_
SETUP_
ACK
RX_OUT_
PACKET_
ACK
TX_
COMPLETE_
ACK
HCAR0
Function
EP0 $1FDD
DIR
DATA
END
FORCE
STALL
TX
PACKET
READY
STALL_
SENT_
ACK
RX_
SETUP_
ACK
RX_OUT_
PACKET_
ACK
TX_
COMPLETE_
ACK
FCAR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT43USB380 | On-The-Go Upgrade of the AT43USB370 USB 2.0 Full-Speed Host/Function Processor |
| AT45BR3214B | 32-MEGABIT DATAFLASH + 4-MEGABIT SRAM STACK MEMORY |
| AT45BR3214B-C1 | 32-MEGABIT DATAFLASH + 4-MEGABIT SRAM STACK MEMORY |
| AT45CS1282 | 128-megabit 2.7-volt Dual-interface Code Shadow DataFlash |
| AT45D011 | 1-Megabit 5.0-volt Only Serial DataFlash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT43USB370 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:USB 2.0 Full-Speed Host/Function Processor |
| AT43USB370E-AC | 功能描述:USB 接口集成電路 USB HOST DEVICE CONTROL - COM TEMP RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| AT43USB380 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:On-The-Go Upgrade of the AT43USB370 USB 2.0 Full-Speed Host/Function Processor |
| AT43USB380E-AC | 功能描述:USB 接口集成電路 USB OTG/HOST/FUNC DEVICE CNTRL RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| AT43USB380E-AI | 功能描述:USB 接口集成電路 USB OTG/HOST/FUNC DEVICE CNTRL RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。