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參數(shù)資料
| 型號： | AT43USB355M-AU |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Full-speed USB Microcontroller with Embedded Hub, ADC and PWM |
| 中文描述： | 8-BIT, MROM, 12 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 1.40 MM, GREEN, PLASTIC, MS-026ACB, LQFP-64 |
| 文件頁數(shù)： | 64/115頁 |
| 文件大?。?/td> | 610K |
| 代理商： | AT43USB355M-AU |
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64
AT43USB355
2603G–USB–04/06
ADC Control and Status Register – ADCSR
Bit 7
–
ADEN: ADC Enable
Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned
off. Turning the ADC off while a conversion is in progress will terminate this conversion.
Bit 6
–
ADSC: ADC Start Conversion
In Single Conversion Mode, a logical “1” must be written to this bit to start each conversion. In
Free Running Mode, a logical “1” must be written to this bit to start the first conversion. The
first time ADSC has been written after the ADC has been enabled or if ADSC is written at the
same time as the ADC is enabled, an extended conversion will precede the initiated conver-
sion. This extended conversion performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is com-
plete, it returns to zero. When a extended conversion precedes a real conversion, ADSC will
stay high until the real conversion completes. Writing a “0” to this bit has no effect.
Bit 5
–
ADFR: ADC Free Running Select
When this bit is set (one), the ADC operates in Free Running Mode. In this mode, the ADC
samples and updates the data registers continuously. Clearing this bit (zero) will terminate
Free Running Mode.
Bit 4
–
ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion completes and the data registers are updated.
The ADC Conversion Complete interrupt is executed if the ADIE bit and the I-bit in SREG are
set (one). ADIF is cleared by the hardware when executing the corresponding interrupt han-
dling vector. Alternatively, ADIF is cleared by writing a logical “1” to the flag. Beware that if
doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if
the SBI and CBI instructions are used.
Bit 3
–
ADIE: ADC Interrupt Enable
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete
interrupt is activated.
Bits 2..0
–
ADPS2..ADPS0: ADC Prescaler Select Bits
These bits determine the division factor between the 2 MHz frequency and the input clock to
the ADC.
Bit
7
6
5
4
3
2
1
0
$07 ($27)
ADEN
ADSC
ADFR
ADIF
ADIE
ADPS2
ADPS1
ADPS0
ADCSR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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