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參數(shù)資料
| 型號： | AT43USB355M-AU |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Full-speed USB Microcontroller with Embedded Hub, ADC and PWM |
| 中文描述： | 8-BIT, MROM, 12 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 1.40 MM, GREEN, PLASTIC, MS-026ACB, LQFP-64 |
| 文件頁數(shù)： | 50/115頁 |
| 文件大小： | 610K |
| 代理商： | AT43USB355M-AU |
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50
AT43USB355
2603G–USB–04/06
Note:
X = A or B
Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written, are
transferred to a temporary location. They are latched when Timer/Counter1 reaches the value
TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an
unsynchronized OCR1A/OCR1B write. See Figure 16 for an example.
Figure 16.
Effects on Unsynchronized OCR1 Latching
Note:
X = A or B
During the time between the write and the latch operation, a read from OCR1A or OCR1B will
read the contents of the temporary location. This means that the most recently written value
always will read out of OCR1A/B
When the OCR1 contains $0000 or TOP, the output OC1A/OC1B is updated to low or high on
the next compare match, according to the settings of COM1A1/COM1A0 or
COM1B1/COM1B0. This is shown in Table 17.
Note: If the compare register contains the TOP value and the prescaler is not in use
(CS12..CS10 = 001), the PWM output will not produce any pulse at all, because up-counting
and down-counting values are reached simultaneously. When the prescaler is in use
Table 16.
Compare1 Mode Select in PWM Mode
COM1X1
COM1X0
Effect on OCX1
0
0
Not connected
0
1
Not connected
1
0
Cleared on compare match, up-counting. Set on compare match,
down-counting (non-inverted PWM).
1
1
Cleared on compare match, down-counting. Set on compare match,
up-counting (inverted PWM).
Synchronized
OCR1X Latch
PWM Output OC1X
Counter Value
Compare Value
PWM Output OC1X
Counter Value
Compare Value
Unsynchronized
OCR1X Latch
Glitch
Compare Value Changes
Compare Value Changes
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