參數(shù)資料
型號: AT43USB355M-AU
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Full-speed USB Microcontroller with Embedded Hub, ADC and PWM
中文描述: 8-BIT, MROM, 12 MHz, RISC MICROCONTROLLER, PQFP64
封裝: 1.40 MM, GREEN, PLASTIC, MS-026ACB, LQFP-64
文件頁數(shù): 8/115頁
文件大?。?/td> 610K
代理商: AT43USB355M-AU
8
AT43USB355
2603G–USB–04/06
The AVR uses a Harvard architecture concept – with separate memories and buses for pro-
gram and data. The program memory is executed with a single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program memory is
a downloadable SRAM or a mask programmed ROM.
With the relative jump and call instructions, the whole 24K address space is directly accessed.
Most AVR instructions have a single 16-bit word format. Every program memory address con-
tains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on
the stack. The stack is effectively allocated in the general data SRAM, and consequently, the
stack size is only limited by the total SRAM size and the usage of the SRAM. All user pro-
grams must initialize the Stack Pointer (SP) in the reset routine (before subroutines or
interrupts are executed). The 10-bit SP is read/write accessible in the I/O space.
The 1-Kbyte data SRAM can be easily accessed through the five different addressing modes
supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps. A flexi-
ble interrupt module has its control registers in the I/O space with an additional global interrupt
enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt
vector table at the beginning of the program memory. The interrupts have priority in accor-
dance with their interrupt vector position. The lower the interrupt vector address, the higher the
priority.
The General-
purpose
Register File
Table 1.
AVR CPU General-purpose Working Register
Register
Address
Comment
R0
$00
R1
$01
R2
$02
..
R13
$0D
R14
$0E
R15
$0F
R16
$10
R17
$11
..
R26
$1A
X-register low byte
R27
$1B
X-register high byte
R28
$1C
Y-register low byte
R29
$1D
Y-register high byte
R30
$1E
Z-register low byte
R31
$1F
Z-register high byte
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