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參數(shù)資料
| 型號： | AT43USB355M-AU |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Full-speed USB Microcontroller with Embedded Hub, ADC and PWM |
| 中文描述： | 8-BIT, MROM, 12 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 1.40 MM, GREEN, PLASTIC, MS-026ACB, LQFP-64 |
| 文件頁數(shù)： | 86/115頁 |
| 文件大小： | 610K |
| 代理商： | AT43USB355M-AU |
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86
AT43USB355
2603G–USB–04/06
Hub End-point 0 Service Routine Register – HCSR0
Function End-point 0 Service Routine Register – FCSR0
Bit 7..4 – Reserved
These bits are reserved in the AT43USB355 and will read as zero.
Bit 3 – STALL SENT
The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses
this bit when responding to a Get Status[End-point] request. It is a read only bit and that is
cleared indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowl-
edge Register.
Bit 2 – RX SETUP: Setup Packet Received
This bit is used by control end-points only to signal to the microcontroller that the USB hard-
ware has received a valid SETUP packet and that the data portion of the packet is stored in
the FIFO. The hardware will clear all other bits in this register while setting RX SETUP. If inter-
rupt is enabled, the microcontroller will be interrupted when RX SETUP is set. After the
completion of reading the data from the FIFO, firmware should clear this bit by writing a one to
the RX_SETUP_ACK bit of the Control and Acknowledge Register.
Bit 1 – RX OUT PACKET
The USB hardware sets this bit after it has stored the data of an OUT transaction in the FIFO.
While this bit is set, the hardware will NAK all OUT tokens. The USB hardware will not over-
write the data in the FIFO except for an early set-up. RX OUT Packet is used for the following
operations:
1.
Control write transactions by a control end-point.
2.
OUT transaction with DATA1 PID to complete the status phase of a control end-point.
Setting this bit causes an interrupt to the microcontroller if the interrupt is enabled. FW clears
this bit after the FIFO contents have been read by writing a one to the
RX_OUT_PACKET_ACK bit of the Control and Acknowledge Register.
Bit 0 – TX COMPL: Transmit Completed
This bit is used by a control end-point hardware to signal to the microcontroller that it has suc-
cessfully completed certain transactions. TX Complete is set at the completion of a:
1.
Control read data stage.
2.
Status stage without data stage.
3.
Status stage after a control write transaction.
This bit is read only and is cleared indirectly by writing a one to the TX_COMPLETE_ACK bit
of the Control and Acknowledge Register.
Bit
7
6
5
4
3
2
1
0
Function EP0 $1FDF
–
–
–
–
STALL SENT
RX SETUP
RX OUT PACKET
TX COMPLETE
HCSR0
Function EP0 $1FDD
–
–
–
–
STALL SENT
RX SETUP
RX OUT PACKET
TX COMPLETE
FCSR0
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
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