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| 型號(hào)： | AT43USB355M-AU |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Full-speed USB Microcontroller with Embedded Hub, ADC and PWM |
| 中文描述： | 8-BIT, MROM, 12 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 1.40 MM, GREEN, PLASTIC, MS-026ACB, LQFP-64 |
| 文件頁(yè)數(shù)： | 54/115頁(yè) |
| 文件大?。?/td> | 610K |
| 代理商： | AT43USB355M-AU |
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54
AT43USB355
2603G–USB–04/06
The interconnection between master and slave CPUs with SPI is shown in Figure 19. The
PB7(SCK) pin is the clock output in the master mode and is the clock input in the slave mode.
Writing to the SPI data register of the master CPU starts the SPI clock generator, and the data
written shifts out of the PB5(MOSI) pin and into the PB5(MOSI) pin of the slave CPU. After
shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If
the SPI interrupt enable bit (SPIE) in the SPCR register is set, an interrupt is requested. The
Slave Select input, PB4(SS), is set low to select an individual slave SPI device. The two shift
registers in the Master and the Slave can be considered as one distributed 16-bit circular shift
register. This is shown in Figure 19. When data is shifted from the master to the slave, data is
also shifted in the opposite direction, simultaneously. This means that during one shift cycle,
data in the master and the slave are interchanged.
Figure 19.
SPI Master/Slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received byte must be
read from the SPI Data Register before the next byte has been completely shifted in. Other-
wise, the first byte is lost.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is overrid-
den according to the following table:
Note:
See “Port B” on page 68 for a detailed description of how to define the direction of the user
defined SPI pins.
SCK
SS
SCK
SS
V
CC
MISO MISO
MOSI MOSI
LSB
MASTER
MSB
8-bit Shift Register
SPI
Clock Generator
LSB
SLAVE
MSB
8-bit Shift Register
Table 19.
SPI Pin Overrides
Pin
Direction, Master SPI
Direction, Slave SPI
MOSI
User Defined
Input
MISO
Input
User Defined
SCK
User Defined
Input
SSN
User Defined
Input
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