參數(shù)資料
型號: AT42QT1060-MMU
廠商: ATMEL CORP
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC28
封裝: 4 X 4 MM, 1MM HEIGHT, 0.45 MM PITCH, ROHS COMPLIANT, MLF-28
文件頁數(shù): 8/32頁
文件大?。?/td> 389K
代理商: AT42QT1060-MMU
16
9505E–AT42–02/09
AT42QT1060
9.
The device resets the internal address to the location indicated by the memory address
sent to it previously. Therefore, there is no need to send the memory address again
when reading from the same location.
5.4
SDA, SCL
The I
2C-compatible bus transmits data and clock with SDA and SCL respectively. They are
open-drain; that is I
2C-compatible master and slave devices can only drive these lines low or
leave them open. The termination resistors (not shown) pull the line up to Vdd if no
I
2C-compatible device is pulling it down.
The termination resistors commonly range from 1 k
to 10 kand should be chosen so that the
rise times on SDA and SCL meet the I2C-compatible specifications (1 s maximum).
Standalone mode: if I
2C-compatible communications are not required, then standalone mode
can be enabled by connecting SDA to Vss and SCL to Vdd. See Section 2.3 on page 5 for more
information.
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