參數(shù)資料
型號(hào)： AT42QT1060-MMU
廠商： ATMEL CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC28
封裝： 4 X 4 MM, 1MM HEIGHT, 0.45 MM PITCH, ROHS COMPLIANT, MLF-28
文件頁(yè)數(shù)： 7/32頁(yè)
文件大小： 389K
代理商： AT42QT1060-MMU
15
9505E–AT42–02/09
AT42QT1060
1.
The host initiates the transfer by sending the START condition
2.
The host follows this by sending the slave address of the device together with the
WRITE bit.
3.
The device sends an ACK.
4.
The host then sends the memory address within the device it wishes to write to.
5.
The device sends an ACK.
6.
The host transmits one or more data bytes; each is acknowledged by the device.
7.
If the host sends more than one data byte, they are written to consecutive memory
addresses.
8.
The device automatically increments the target memory address after writing each data
byte.
9.
After writing the last data byte, the host should send the STOP condition.
Note: the host should not try to write beyond address 255 because this is the limit of the device’s
internal memory address.
5.3.2
Reading Data From the Device
The sequence of events required to read data from the device is shown next.
1.
The host initiates the transfer by sending the START condition
2.
The host follows this by sending the slave address of the device together with the
WRITE bit.
3.
The device sends an ACK.
4.
The host then sends the memory address within the device it wishes to read from.
5.
The device sends an ACK.
6.
The host must then send a STOP and a START condition followed by the slave address
again but this time accompanied by the READ bit.
7.
The device returns an ACK, followed by a data byte.
8.
The host must return either an ACK or NACK.
a.
If the host returns an ACK, the device subsequently transmits the data byte from
the next address. Each time a data byte is transmitted, the device automatically
increments the internal address. The device continues to return data bytes until the
host responds with a NACK.
b.
STOP condition.
Target memory address within device
Data
Data to be written
P
Stop condition
Table 5-1.
Description of Write Data Bits
Key
Description
SLA+W
MemAddress
AA
S
SLA+R
A
P
Host to Device
Device to Host
P
A
/A
Data 1
Data 2
Data n
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