參數資料
型號: AT42QT1060-MMU
廠商: ATMEL CORP
元件分類: 模擬信號調理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC28
封裝: 4 X 4 MM, 1MM HEIGHT, 0.45 MM PITCH, ROHS COMPLIANT, MLF-28
文件頁數: 5/32頁
文件大小: 389K
代理商: AT42QT1060-MMU
13
9505E–AT42–02/09
AT42QT1060
4.5
Data Packet Format
All data packets are 9 bits long, consisting of one data byte and an acknowledge bit. During a
data transfer, the host generates the clock and the START and STOP conditions, while the
Receiver is responsible for acknowledging the reception. An acknowledge (ACK) is signaled by
the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA
line high, a NACK is signaled.
4.6
Combining Address and Data Packets Into a Transmission
A transmission consists of a START condition, an SLA+R/W, one or more data packets and a
STOP condition. The wired-ANDing of the SCL line is used to implement handshaking between
the host and the device. The device extends the SCL low period by pulling the SCL line low
whenever it needs extra time for processing between the data transmissions.
Holding down either SCL or SDA for clock stretching or any other purpose will slow down the
operation of the QT2160. If SCL or SDA is continuously held low for more than ~12ms, this will
be deemed as a error condition and the I2C-compatible unit reset.
Note: Each write or read cycle must end with a STOP condition. The QT2160 may not respond
correctly if a cycle is terminated by a new START condition.
Figure 4-7 shows a typical data transmission. Note that several data bytes can be transmitted
between the SLA+R/W and the STOP.
Figure 4-6.
Data Packet Format
Figure 4-7.
Packet Transmission
SCL from
Master
SLA+R/W
12
7
8
9
SDA from
Transmitter
Aggregate
SDA
Data MSB
Data LSB
ACK
Data Byte
SDA from
Receiver
STOP or
Next Data Byte
12
7
8
9
12
7
8
9
Data MSB
Data LSB
ACK
Data Byte
STOP
SDA
SCL
Addr MSB
Addr LSB
R/W
ACK
START
SLA+R/W
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