參數(shù)資料
型號: AT42QT1060-MMU
廠商: ATMEL CORP
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC28
封裝: 4 X 4 MM, 1MM HEIGHT, 0.45 MM PITCH, ROHS COMPLIANT, MLF-28
文件頁數(shù): 3/32頁
文件大?。?/td> 389K
代理商: AT42QT1060-MMU
11
9505E–AT42–02/09
AT42QT1060
4.
I2C-compatible Bus Operation
4.1
Interface Bus
More detailed information about the I2C-compatible bus protocol is available from
www.i2C-bus.org. Devices are connected onto the I2C-compatible bus as shown in Figure 4-1.
Both bus lines are connected to Vdd via pull-up resistors. The bus drivers of all I2C-compatible
devices must be open-drain type. This implements a wired-AND function which allows any and
all devices to drive the bus, one at a time. A low level on the bus is generated when a device
outputs a zero.
Figure 4-1.
I2C
-compatible Interface Bus
4.2
Transferring Data Bits
Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the
data line must be stable when the clock line is high; The only exception to this rule is for
generating START and STOP conditions.
Table 4-2.
I2C
-compatible Bus Specifications
Parameter
Unit
Address space
7-bit
Maximum bus speed (SCL)
100 kHz
Hold time START condition
4 s minimum
Setup time for STOP condition
4 s minimum
Bus free time between a STOP and START condition
4.7 s minimum
Rise times on SDA and SCL
1 s maximum
Vdd
Device 1
Device 2
Device 3
Device n
R1
R2
SDA
SCL
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