- 您現(xiàn)在的位置：買賣IC網 > PDF目錄381395 > AT17LV010A (Atmel Corp.) 1M FPGA Configuration EEPROM Memory(1M 現(xiàn)場可編程門陣列（FPGA）配置EEPROM存儲器) PDF資料下載
參數(shù)資料
| 型號： | AT17LV010A |
| 廠商： | Atmel Corp. |
| 英文描述： | 1M FPGA Configuration EEPROM Memory(1M 現(xiàn)場可編程門陣列（FPGA）配置EEPROM存儲器) |
| 中文描述： | 100萬FPGA配置存儲器（100萬現(xiàn)場可編程門陣列（FPGA）的配置的EEPROM存儲器） |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 205K |
| 代理商： | AT17LV010A |
AT17C/LV512A/010A
5
Pin Configurations
20
PLCC
Pin
Name
I/O
Description
2
DATA
I/O
Three-state data output for configuration. Open-collector bi-directional pin for programming.
4
DCLK
I/O
Clock output or clock input. Rising edges on DCLK increment the internal address counter and present the
next bit of data to the DATA pin. The counter is incremented only if the OE input is held High, the nCS input
is held Low, and all configuration data has not been transferred to the target device (otherwise, as the
master device, the DCLK pin drives Low).
5
WP1
I
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by default due
to internal pull-down resistor. This input pin is not used during FPGA loading operations. See
programming specifications for details.
8
OE
I
Output enable (active High) and reset (active Low) when SER_EN is High. A Low logic level resets the
address counter. A High logic level (with nCS Low) enables DATA and permits the address counter to
count. In the mode, if this pin is Low (reset), the internal oscillator becomes inactive and DCLK drives Low.
The logic polarity of this input is programmable and must be programmed active High (RESET active Low)
by the user during programming for Altera applications.
9
nCS
I
Chip select input (active Low). A Low input (with OE High) allows DCLK to increment the address counter
and enables DATA to drive out. If the AT17A Series is reset with nCS Low, the device initializes as the first
(and master) device in a daisy-chain. If the AT17A Series is reset with nCS High, the device initializes as a
subsequent AT17A Series device in the chain.
10
GND
Ground pin. A 0.2
μF decoupling capacitor should be placed between the VCC and GND pins.
12
nCASC
O
Cascade select output (active Low). This output goes Low when the address counter has reached its
maximum value. In a daisy-chain of AT17A Series devices, the nCASC pin of one device is usually
connected to the nCS input pin of the next device in the chain, which permits DCLK from the master
Configurator to clock data from a subsequent AT17A Series device in the chain.
A2
I
Device selection input, A2. This is used to enable (or select) the device during programming, (i.e., when
SER_EN is Low; please refer to the “Programming Specification” application note for more details).
15
READY
O
Open collector reset state indicator. Driven Low during power-up reset, released (tri-stated) when
power-up is complete. (Recommend a 4.7 k
pull-up on this pin if used).
18
SER_EN
I
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low, enables the
2-wire serial programming mode.
20
VCC
+3.3V/+5V power supply pin
Absolute Maximum Ratings*
Operating Temperature.................................. -55
°
C to +125
°
C
*NOTICE:
Stresses beyond those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum
Ratings conditions for extended periods of time
may affect device reliability.
Storage Temperature..................................... -65
°
C to +150
°
C
Voltage on Any Pin
with Respect to Ground..............................-0.1V to V
CC
+0.5V
Supply Voltage (V
CC
) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec @ 1/16 in.)..............260
°
C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100 pF)................................ 2000V
相關PDF資料 |
PDF描述 |
|---|---|
| AT17C010 | 1M FPGA Configuration EEPROM Memory(1M 現(xiàn)場可編程（FPGA）配置EEPROM存儲器) |
| AT17C020A | FPGA Configuration EEPROM Memory |
| AT17C002A-10JC | FPGA Configuration EEPROM Memory |
| AT17LV020A | FPGA Configuration EEPROM Memory |
| AT17LV512A | FPGA Configuration EEPROM Memory |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV010A-10BJC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10CC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A10JC | 制造商:Atmel Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。