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參數(shù)資料
| 型號(hào)： | AT17LV010A |
| 廠商： | Atmel Corp. |
| 英文描述： | 1M FPGA Configuration EEPROM Memory(1M 現(xiàn)場(chǎng)可編程門陣列（FPGA）配置EEPROM存儲(chǔ)器) |
| 中文描述： | 100萬(wàn)FPGA配置存儲(chǔ)器（100萬(wàn)現(xiàn)場(chǎng)可編程門陣列（FPGA）的配置的EEPROM存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 10/13頁(yè) |
| 文件大?。?/td> | 205K |
| 代理商： | AT17LV010A |
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AT17C/LV512A/010A
10
AC Characteristics for AT17LV512A/010A
V
CC
= 3.3V
± 10% Commercial / V
CC
= 3.3V ± 10% Ind./Mil.
Notes:
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3.
Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
Symbol
Description
Commercial
Industrial/Military
(1)
Units
Min
Max
Min
Max
T
OE
(2)
OE to Data Delay
50
55
ns
T
CE
(2)
nCS to Data Delay
55
60
ns
T
CAC
(2)
DCLK to Data Delay
60
65
ns
T
OH
Data Hold From nCS, OE, or DCLK
0
0
ns
T
DF
(3)
nCS or OE to Data Float Delay
50
50
ns
T
LC
DCLK Low Time Slave Mode
25
25
ns
T
HC
DCLK High Time Slave Mode
25
25
ns
T
SCE
nCS Setup Time to DCLK (to guarantee proper counting)
35
40
ns
T
HCE
nCS Hold Time from DCLK (to guarantee proper
counting)
0
0
ns
T
LOE
OE Low Time (guarantees counter is reset)
20
20
ns
F
MAX
MAX Input Clock Frequency Slave Mode
15
10
MHz
T
LC
DCLK Low Time Master Mode
30
300
30
300
ns
T
HC
DCLK High Time Master Mode
30
300
30
300
ns
V
RDY
Ready Pin Open Collector Voltage
1.2
2.4
1.2
2.4
V
AC Characteristics for AT17LV512A/010A When Cascading
V
CC
= 3.3V ± 10% Commercial / V
CC
= 3.3V ± 10% Ind./Mil.
Symbol
Description
Commercial
Industrial/Military
(1)
Units
Min
Max
Min
Max
T
CDF
(3)
DCLK to Data Float Delay
50
50
ns
T
OCK
(2)
DCLK to nCASC Delay
50
55
ns
T
OCE
(2)
nCS to nCASC Delay
35
40
ns
T
OOE
(2)
OE to nCASC Delay
35
35
ns
F
MAX
MAX Input Clock Frequency Slave Mode
12.5
10
MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT17C010 | 1M FPGA Configuration EEPROM Memory(1M 現(xiàn)場(chǎng)可編程（FPGA）配置EEPROM存儲(chǔ)器) |
| AT17C020A | FPGA Configuration EEPROM Memory |
| AT17C002A-10JC | FPGA Configuration EEPROM Memory |
| AT17LV020A | FPGA Configuration EEPROM Memory |
| AT17LV512A | FPGA Configuration EEPROM Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV010A-10BJC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10CC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A10JC | 制造商:Atmel Corporation 功能描述: |
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