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參數資料
| 型號： | AT17LV010A |
| 廠商： | Atmel Corp. |
| 英文描述： | 1M FPGA Configuration EEPROM Memory(1M 現場可編程門陣列（FPGA）配置EEPROM存儲器) |
| 中文描述： | 100萬FPGA配置存儲器（100萬現場可編程門陣列（FPGA）的配置的EEPROM存儲器） |
| 文件頁數： | 3/13頁 |
| 文件大小： | 205K |
| 代理商： | AT17LV010A |
AT17C/LV512A/010A
3
FPGA Device Configuration
FPGA devices can be configured with an AT17A Series
EEPROM as shown in Figure 1. The AT17A Series device
stores configuration data in its EEPROM array and clocks
the data out serially with its internal oscillator. The OE,
nCS, and DCLK pins supply the control signals for the
address counter and the output tri-state buffer. The AT17A
Series device sends a serial bitstream of configuration data
to its DATA pin, which is connected to the DATA0 input pin
on the FPGA device.
When configuration data for an FPGA device exceeds the
capacity of a single AT17A Series device, multiple AT17A
Series devices can be serially linked together (Figure 2).
When multiple AT17A Series devices are required, the
nCASC and nCS pins provide handshaking between the
cascaded EEPROMs.
The position of an AT17A Series device in a chain deter-
mines its operation. The first AT17A Series device in a
Configurator chain is powered up or reset with nCS Low
and is configured for the FPGA device’s protocol. This
AT17A Series device supplies all clock pulses to one or
more FPGA devices and to any downstream AT17A Series
Configurator during configuration. The first AT17A Series
Configurator also provides the first stream of data to the
FPGA devices during multi-device configuration. Once the
first AT17A Series device finishes sending configuration
data, it drives its nCASC pin Low, which drives the nCS pin
of the second AT17A Series device Low. This activates the
second AT17A Series device to send configuration data to
the FPGA device.
The first AT17A Series device clocks all subsequent
AT17A Series devices until configuration is complete. Once
all configuration data is transferred and nCS on the first
AT17A Series device is driven High by CONF_DONE on
the FPGA devices, the first AT17A Series device clocks 16
additional cycles to initialize the FPGA device before going
into zero-power (idle) state. If nCS on the first AT17A
Series device is driven High before all configuration data is
transferred–or if the nCS is not driven High after all configu-
ration data is transferred– nSTATUS is driven Low,
indicating a configuration error.
The READY pin is available as an open-collector indicator
of the device’s reset status; it is driven Low while the device
is in its power-on reset cycle and released (tri-stated) when
the cycle is complete. It can be used to hold the FPGA
device in reset while it is completing its power-on reset but
it cannot be used to effectively delay configuration (i.e., the
output is released well before the system VCC has
stabilized).
Figure 1.
Configuration with a Single AT17A Series Configurator
Notes:
1. 1.0 k
resistors used unless otherwise specified.
2. Applicable to EPF6K.
3. Use of the READY pin is optional.
4. Introducing a RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
5. Reset polarity of EEPROM must be set active Low (OE active High).
MSEL1
nSTATUS
MSEL0
CONF_DONE
DATA0
DCLK
nCONFIG
EPF10K
AT17C512A/010A
AT17LV512A/010A
GND
OE
nCS
DATA
DCLK
nCE
VCC
VCC
VCC
READY
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相關代理商/技術參數 |
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| AT17LV010A-10BJC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10CC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV010A10JC | 制造商:Atmel Corporation 功能描述: |
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